mirror of
https://gitlab.com/pulsechaincom/erigon-pulse.git
synced 2024-12-28 14:47:16 +00:00
1203c6a237
* crypto/bn256: full switchover to cloudflare's code * crypto/bn256: only use cloudflare for optimized architectures * crypto/bn256: upstream fallback for non-optimized code * .travis, build: drop support for Go 1.8 (need type aliases) * crypto/bn256/cloudflare: enable curve mul lattice optimization
182 lines
3.0 KiB
C
182 lines
3.0 KiB
C
#define mul(a0,a1,a2,a3, rb, stack) \
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MOVQ a0, AX \
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MULQ 0+rb \
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MOVQ AX, R8 \
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MOVQ DX, R9 \
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MOVQ a0, AX \
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MULQ 8+rb \
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ADDQ AX, R9 \
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ADCQ $0, DX \
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MOVQ DX, R10 \
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MOVQ a0, AX \
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MULQ 16+rb \
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ADDQ AX, R10 \
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ADCQ $0, DX \
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MOVQ DX, R11 \
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MOVQ a0, AX \
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MULQ 24+rb \
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ADDQ AX, R11 \
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ADCQ $0, DX \
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MOVQ DX, R12 \
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\
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storeBlock(R8,R9,R10,R11, 0+stack) \
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MOVQ R12, 32+stack \
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\
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MOVQ a1, AX \
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MULQ 0+rb \
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MOVQ AX, R8 \
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MOVQ DX, R9 \
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MOVQ a1, AX \
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MULQ 8+rb \
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ADDQ AX, R9 \
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ADCQ $0, DX \
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MOVQ DX, R10 \
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MOVQ a1, AX \
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MULQ 16+rb \
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ADDQ AX, R10 \
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ADCQ $0, DX \
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MOVQ DX, R11 \
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MOVQ a1, AX \
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MULQ 24+rb \
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ADDQ AX, R11 \
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ADCQ $0, DX \
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MOVQ DX, R12 \
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\
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ADDQ 8+stack, R8 \
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ADCQ 16+stack, R9 \
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ADCQ 24+stack, R10 \
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ADCQ 32+stack, R11 \
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ADCQ $0, R12 \
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storeBlock(R8,R9,R10,R11, 8+stack) \
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MOVQ R12, 40+stack \
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\
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MOVQ a2, AX \
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MULQ 0+rb \
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MOVQ AX, R8 \
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MOVQ DX, R9 \
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MOVQ a2, AX \
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MULQ 8+rb \
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ADDQ AX, R9 \
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ADCQ $0, DX \
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MOVQ DX, R10 \
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MOVQ a2, AX \
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MULQ 16+rb \
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ADDQ AX, R10 \
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ADCQ $0, DX \
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MOVQ DX, R11 \
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MOVQ a2, AX \
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MULQ 24+rb \
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ADDQ AX, R11 \
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ADCQ $0, DX \
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MOVQ DX, R12 \
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\
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ADDQ 16+stack, R8 \
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ADCQ 24+stack, R9 \
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ADCQ 32+stack, R10 \
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ADCQ 40+stack, R11 \
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ADCQ $0, R12 \
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storeBlock(R8,R9,R10,R11, 16+stack) \
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MOVQ R12, 48+stack \
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\
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MOVQ a3, AX \
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MULQ 0+rb \
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MOVQ AX, R8 \
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MOVQ DX, R9 \
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MOVQ a3, AX \
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MULQ 8+rb \
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ADDQ AX, R9 \
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ADCQ $0, DX \
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MOVQ DX, R10 \
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MOVQ a3, AX \
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MULQ 16+rb \
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ADDQ AX, R10 \
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ADCQ $0, DX \
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MOVQ DX, R11 \
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MOVQ a3, AX \
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MULQ 24+rb \
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ADDQ AX, R11 \
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ADCQ $0, DX \
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MOVQ DX, R12 \
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\
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ADDQ 24+stack, R8 \
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ADCQ 32+stack, R9 \
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ADCQ 40+stack, R10 \
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ADCQ 48+stack, R11 \
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ADCQ $0, R12 \
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storeBlock(R8,R9,R10,R11, 24+stack) \
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MOVQ R12, 56+stack
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#define gfpReduce(stack) \
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\ // m = (T * N') mod R, store m in R8:R9:R10:R11
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MOVQ ·np+0(SB), AX \
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MULQ 0+stack \
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MOVQ AX, R8 \
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MOVQ DX, R9 \
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MOVQ ·np+0(SB), AX \
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MULQ 8+stack \
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ADDQ AX, R9 \
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ADCQ $0, DX \
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MOVQ DX, R10 \
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MOVQ ·np+0(SB), AX \
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MULQ 16+stack \
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ADDQ AX, R10 \
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ADCQ $0, DX \
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MOVQ DX, R11 \
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MOVQ ·np+0(SB), AX \
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MULQ 24+stack \
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ADDQ AX, R11 \
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\
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MOVQ ·np+8(SB), AX \
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MULQ 0+stack \
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MOVQ AX, R12 \
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MOVQ DX, R13 \
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MOVQ ·np+8(SB), AX \
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MULQ 8+stack \
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ADDQ AX, R13 \
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ADCQ $0, DX \
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MOVQ DX, R14 \
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MOVQ ·np+8(SB), AX \
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MULQ 16+stack \
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ADDQ AX, R14 \
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\
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ADDQ R12, R9 \
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ADCQ R13, R10 \
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ADCQ R14, R11 \
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\
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MOVQ ·np+16(SB), AX \
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MULQ 0+stack \
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MOVQ AX, R12 \
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MOVQ DX, R13 \
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MOVQ ·np+16(SB), AX \
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MULQ 8+stack \
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ADDQ AX, R13 \
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\
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ADDQ R12, R10 \
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ADCQ R13, R11 \
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\
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MOVQ ·np+24(SB), AX \
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MULQ 0+stack \
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ADDQ AX, R11 \
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\
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storeBlock(R8,R9,R10,R11, 64+stack) \
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\
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\ // m * N
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mul(·p2+0(SB),·p2+8(SB),·p2+16(SB),·p2+24(SB), 64+stack, 96+stack) \
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\
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\ // Add the 512-bit intermediate to m*N
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loadBlock(96+stack, R8,R9,R10,R11) \
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loadBlock(128+stack, R12,R13,R14,R15) \
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\
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MOVQ $0, AX \
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ADDQ 0+stack, R8 \
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ADCQ 8+stack, R9 \
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ADCQ 16+stack, R10 \
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ADCQ 24+stack, R11 \
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ADCQ 32+stack, R12 \
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ADCQ 40+stack, R13 \
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ADCQ 48+stack, R14 \
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ADCQ 56+stack, R15 \
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ADCQ $0, AX \
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\
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gfpCarry(R12,R13,R14,R15,AX, R8,R9,R10,R11,BX)
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