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clk: imx8mp: inform CCF of maximum frequency of clocks
The IMX8MPCEC datasheet lists maximum frequencies allowed for different modules. Some of these limits are universal, but some depend on whether the SoC is operating in nominal or in overdrive mode. The imx8mp.dtsi currently assumes overdrive mode and configures some clocks in accordance with this. Boards wishing to make use of nominal mode will need to override some of the clock rates manually. As operating the clocks outside of their allowed range can lead to difficult to debug issues, it makes sense to register the maximum rates allowed in the driver, so the CCF can take them into account. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.kernel.org/r/20250218-imx8m-clk-v4-6-b7697dc2dcd0@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
This commit is contained in:
Ahmad Fatoum
Abel Vesa
parent
d5992f1af1
commit
06a61b5cb6
@ -8,6 +8,7 @@
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/units.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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@ -406,11 +407,151 @@ static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_
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static struct clk_hw **hws;
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static struct clk_hw_onecell_data *clk_hw_data;
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struct imx8mp_clock_constraints {
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unsigned int clkid;
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u32 maxrate;
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};
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/*
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* Below tables are taken from IMX8MPCEC Rev. 2.1, 07/2023
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* Table 13. Maximum frequency of modules.
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* Probable typos fixed are marked with a comment.
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*/
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static const struct imx8mp_clock_constraints imx8mp_clock_common_constraints[] = {
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{ IMX8MP_CLK_A53_DIV, 1000 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ENET_AXI, 266666667 }, /* Datasheet claims 266MHz */
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{ IMX8MP_CLK_NAND_USDHC_BUS, 266666667 }, /* Datasheet claims 266MHz */
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{ IMX8MP_CLK_MEDIA_APB, 200 * HZ_PER_MHZ },
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{ IMX8MP_CLK_HDMI_APB, 133333333 }, /* Datasheet claims 133MHz */
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{ IMX8MP_CLK_ML_AXI, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_AHB, 133333333 },
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{ IMX8MP_CLK_IPG_ROOT, 66666667 },
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{ IMX8MP_CLK_AUDIO_AHB, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_DISP2_PIX, 170 * HZ_PER_MHZ },
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{ IMX8MP_CLK_DRAM_ALT, 666666667 },
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{ IMX8MP_CLK_DRAM_APB, 200 * HZ_PER_MHZ },
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{ IMX8MP_CLK_CAN1, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_CAN2, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_PCIE_AUX, 10 * HZ_PER_MHZ },
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{ IMX8MP_CLK_I2C5, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_I2C6, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_SAI1, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_SAI2, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_SAI3, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_SAI5, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_SAI6, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_ENET_QOS, 125 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ENET_QOS_TIMER, 200 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ENET_REF, 125 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ENET_TIMER, 125 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ENET_PHY_REF, 125 * HZ_PER_MHZ },
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{ IMX8MP_CLK_NAND, 500 * HZ_PER_MHZ },
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{ IMX8MP_CLK_QSPI, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_USDHC1, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_USDHC2, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_I2C1, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_I2C2, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_I2C3, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_I2C4, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_UART1, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_UART2, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_UART3, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_UART4, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ECSPI1, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ECSPI2, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_PWM1, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_PWM2, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_PWM3, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_PWM4, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_GPT1, 100 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPT2, 100 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPT3, 100 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPT4, 100 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPT5, 100 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPT6, 100 * HZ_PER_MHZ },
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{ IMX8MP_CLK_WDOG, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_IPP_DO_CLKO1, 200 * HZ_PER_MHZ },
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{ IMX8MP_CLK_IPP_DO_CLKO2, 200 * HZ_PER_MHZ },
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{ IMX8MP_CLK_HDMI_REF_266M, 266 * HZ_PER_MHZ },
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{ IMX8MP_CLK_USDHC3, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_MIPI_PHY1_REF, 300 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_DISP1_PIX, 250 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_CAM2_PIX, 277 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_LDB, 595 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE, 200 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ECSPI3, 80 * HZ_PER_MHZ },
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{ IMX8MP_CLK_PDM, 200 * HZ_PER_MHZ },
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{ IMX8MP_CLK_SAI7, 66666667 }, /* Datasheet claims 66MHz */
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{ IMX8MP_CLK_MAIN_AXI, 400 * HZ_PER_MHZ },
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{ /* Sentinel */ }
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};
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static const struct imx8mp_clock_constraints imx8mp_clock_nominal_constraints[] = {
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{ IMX8MP_CLK_M7_CORE, 600 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ML_CORE, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU3D_CORE, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU3D_SHADER_CORE, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU2D_CORE, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_AUDIO_AXI_SRC, 600 * HZ_PER_MHZ },
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{ IMX8MP_CLK_HSIO_AXI, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_ISP, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_BUS, 600 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_AXI, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_HDMI_AXI, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU_AXI, 600 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU_AHB, 300 * HZ_PER_MHZ },
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{ IMX8MP_CLK_NOC, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_NOC_IO, 600 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ML_AHB, 300 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_G1, 600 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_G2, 500 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_CAM1_PIX, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_VC8000E, 400 * HZ_PER_MHZ }, /* Datasheet claims 500MHz */
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{ IMX8MP_CLK_DRAM_CORE, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GIC, 400 * HZ_PER_MHZ },
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{ /* Sentinel */ }
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};
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static const struct imx8mp_clock_constraints imx8mp_clock_overdrive_constraints[] = {
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{ IMX8MP_CLK_M7_CORE, 800 * HZ_PER_MHZ},
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{ IMX8MP_CLK_ML_CORE, 1000 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU3D_CORE, 1000 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU3D_SHADER_CORE, 1000 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU2D_CORE, 1000 * HZ_PER_MHZ },
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{ IMX8MP_CLK_AUDIO_AXI_SRC, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_HSIO_AXI, 500 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_ISP, 500 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_BUS, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_AXI, 500 * HZ_PER_MHZ },
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{ IMX8MP_CLK_HDMI_AXI, 500 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU_AXI, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GPU_AHB, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_NOC, 1000 * HZ_PER_MHZ },
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{ IMX8MP_CLK_NOC_IO, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_ML_AHB, 400 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_G1, 800 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_G2, 700 * HZ_PER_MHZ },
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{ IMX8MP_CLK_MEDIA_CAM1_PIX, 500 * HZ_PER_MHZ },
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{ IMX8MP_CLK_VPU_VC8000E, 500 * HZ_PER_MHZ }, /* Datasheet claims 400MHz */
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{ IMX8MP_CLK_DRAM_CORE, 1000 * HZ_PER_MHZ },
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{ IMX8MP_CLK_GIC, 500 * HZ_PER_MHZ },
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{ /* Sentinel */ }
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};
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static void imx8mp_clocks_apply_constraints(const struct imx8mp_clock_constraints constraints[])
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{
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const struct imx8mp_clock_constraints *constr;
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for (constr = constraints; constr->clkid; constr++)
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clk_hw_set_rate_range(hws[constr->clkid], 0, constr->maxrate);
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}
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static int imx8mp_clocks_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np;
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void __iomem *anatop_base, *ccm_base;
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const char *opmode;
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int err;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
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@ -715,6 +856,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
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imx_check_clk_hws(hws, IMX8MP_CLK_END);
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imx8mp_clocks_apply_constraints(imx8mp_clock_common_constraints);
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err = of_property_read_string(np, "fsl,operating-mode", &opmode);
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if (!err) {
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if (!strcmp(opmode, "nominal"))
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imx8mp_clocks_apply_constraints(imx8mp_clock_nominal_constraints);
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else if (!strcmp(opmode, "overdrive"))
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imx8mp_clocks_apply_constraints(imx8mp_clock_overdrive_constraints);
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}
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err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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if (err < 0) {
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dev_err(dev, "failed to register hws for i.MX8MP\n");
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