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coresight-tpdm: Add support to select lane

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TPDM MCMB subunits supports up to 8 lanes CMB. For MCMB
configurations, the field "XTRIG_LNSEL" in CMB_CR register selects
which lane participates in the output pattern mach cross trigger
mechanism governed by the M_CMB_DXPR and M_CMB_XPMR regisers.

Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250226064008.2531037-3-quic_jinlmao@quicinc.com
This commit is contained in:
Tao Zhang 2025-02-25 22:40:07 -08:00 committed by Suzuki K Poulose
parent ee39dbe939
commit 07f7c21745
3 changed files with 62 additions and 0 deletions
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8
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
View File

@ -257,3 +257,11 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t
Description:
(RW) Set/Get the MSR(mux select register) for the CMB subunit
TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane
Date: Feb 2025
KernelVersion 6.15
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Description:
(RW) Set/Get which lane participates in the output pattern
match cross trigger mechanism for the MCMB subunit TPDM.

51
drivers/hwtracing/coresight/coresight-tpdm.c
View File

@ -252,6 +252,18 @@ static umode_t tpdm_cmb_msr_is_visible(struct kobject *kobj,
return 0;
}
static umode_t tpdm_mcmb_is_visible(struct kobject *kobj,
struct attribute *attr, int n)
{
struct device *dev = kobj_to_dev(kobj);
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
if (drvdata && tpdm_has_mcmb_dataset(drvdata))
return attr->mode;
return 0;
}
static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata)
{
if (tpdm_has_dsb_dataset(drvdata)) {
@ -1020,6 +1032,34 @@ static ssize_t cmb_trig_ts_store(struct device *dev,
}
static DEVICE_ATTR_RW(cmb_trig_ts);
static ssize_t mcmb_trig_lane_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
return sysfs_emit(buf, "%u\n",
(unsigned int)drvdata->cmb->mcmb.trig_lane);
}
static ssize_t mcmb_trig_lane_store(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t size)
{
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_MCMB_MAX_LANES))
return -EINVAL;
guard(spinlock)(&drvdata->spinlock);
drvdata->cmb->mcmb.trig_lane = val;
return size;
}
static DEVICE_ATTR_RW(mcmb_trig_lane);
static struct attribute *tpdm_dsb_edge_attrs[] = {
&dev_attr_ctrl_idx.attr,
&dev_attr_ctrl_val.attr,
@ -1182,6 +1222,11 @@ static struct attribute *tpdm_cmb_msr_attrs[] = {
NULL,
};
static struct attribute *tpdm_mcmb_attrs[] = {
&dev_attr_mcmb_trig_lane.attr,
NULL,
};
static struct attribute *tpdm_dsb_attrs[] = {
&dev_attr_dsb_mode.attr,
&dev_attr_dsb_trig_ts.attr,
@ -1248,6 +1293,11 @@ static struct attribute_group tpdm_cmb_msr_grp = {
.name = "cmb_msr",
};
static struct attribute_group tpdm_mcmb_attr_grp = {
.attrs = tpdm_mcmb_attrs,
.is_visible = tpdm_mcmb_is_visible,
};
static const struct attribute_group *tpdm_attr_grps[] = {
&tpdm_attr_grp,
&tpdm_dsb_attr_grp,
@ -1259,6 +1309,7 @@ static const struct attribute_group *tpdm_attr_grps[] = {
&tpdm_cmb_trig_patt_grp,
&tpdm_cmb_patt_grp,
&tpdm_cmb_msr_grp,
&tpdm_mcmb_attr_grp,
NULL,
};

3
drivers/hwtracing/coresight/coresight-tpdm.h
View File

@ -45,6 +45,9 @@
/* MAX number of DSB MSR */
#define TPDM_CMB_MAX_MSR 32
/* MAX lanes in the output pattern for MCMB configurations*/
#define TPDM_MCMB_MAX_LANES 8
/* DSB Subunit Registers */
#define TPDM_DSB_CR (0x780)
#define TPDM_DSB_TIER (0x784)