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media: ipu6: Fix DMA and physical address debugging messages for 32-bit
Fix printing DMA and physical address printing on 32-bit platforms, by using correct types. Also cast DMA_BIT_MASK() result to dma_addr_t to make Clang happy. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Reviewed-by: Bingbu Cao <bingbu.cao@intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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@ -428,11 +428,12 @@ static int ipu6_dma_map_sg(struct device *dev, struct scatterlist *sglist,
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iova_addr = iova->pfn_lo;
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for_each_sg(sglist, sg, count, i) {
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phys_addr_t iova_pa;
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int ret;
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dev_dbg(dev, "mapping entry %d: iova 0x%llx phy %pad size %d\n",
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i, PFN_PHYS(iova_addr), &sg_dma_address(sg),
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sg_dma_len(sg));
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iova_pa = PFN_PHYS(iova_addr);
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dev_dbg(dev, "mapping entry %d: iova %pap phy %pap size %d\n",
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i, &iova_pa, &sg_dma_address(sg), sg_dma_len(sg));
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ret = ipu6_mmu_map(mmu->dmap->mmu_info, PFN_PHYS(iova_addr),
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sg_dma_address(sg),
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@ -97,13 +97,15 @@ static void page_table_dump(struct ipu6_mmu_info *mmu_info)
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for (l1_idx = 0; l1_idx < ISP_L1PT_PTES; l1_idx++) {
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u32 l2_idx;
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u32 iova = (phys_addr_t)l1_idx << ISP_L1PT_SHIFT;
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phys_addr_t l2_phys;
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if (mmu_info->l1_pt[l1_idx] == mmu_info->dummy_l2_pteval)
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continue;
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l2_phys = TBL_PHYS_ADDR(mmu_info->l1_pt[l1_idx];)
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dev_dbg(mmu_info->dev,
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"l1 entry %u; iovas 0x%8.8x-0x%8.8x, at %pa\n",
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l1_idx, iova, iova + ISP_PAGE_SIZE,
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TBL_PHYS_ADDR(mmu_info->l1_pt[l1_idx]));
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"l1 entry %u; iovas 0x%8.8x-0x%8.8x, at %pap\n",
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l1_idx, iova, iova + ISP_PAGE_SIZE, &l2_phys);
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for (l2_idx = 0; l2_idx < ISP_L2PT_PTES; l2_idx++) {
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u32 *l2_pt = mmu_info->l2_pts[l1_idx];
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@ -227,7 +229,7 @@ static u32 *alloc_l1_pt(struct ipu6_mmu_info *mmu_info)
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}
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mmu_info->l1_pt_dma = dma >> ISP_PADDR_SHIFT;
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dev_dbg(mmu_info->dev, "l1 pt %p mapped at %llx\n", pt, dma);
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dev_dbg(mmu_info->dev, "l1 pt %p mapped at %pad\n", pt, &dma);
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return pt;
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@ -330,8 +332,8 @@ static int __ipu6_mmu_map(struct ipu6_mmu_info *mmu_info, unsigned long iova,
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u32 iova_end = ALIGN(iova + size, ISP_PAGE_SIZE);
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dev_dbg(mmu_info->dev,
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"mapping iova 0x%8.8x--0x%8.8x, size %zu at paddr 0x%10.10llx\n",
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iova_start, iova_end, size, paddr);
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"mapping iova 0x%8.8x--0x%8.8x, size %zu at paddr %pap\n",
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iova_start, iova_end, size, &paddr);
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return l2_map(mmu_info, iova_start, paddr, size);
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}
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@ -361,10 +363,13 @@ static size_t l2_unmap(struct ipu6_mmu_info *mmu_info, unsigned long iova,
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for (l2_idx = (iova_start & ISP_L2PT_MASK) >> ISP_L2PT_SHIFT;
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(iova_start & ISP_L1PT_MASK) + (l2_idx << ISP_PAGE_SHIFT)
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< iova_start + size && l2_idx < ISP_L2PT_PTES; l2_idx++) {
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phys_addr_t pteval;
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l2_pt = mmu_info->l2_pts[l1_idx];
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pteval = TBL_PHYS_ADDR(l2_pt[l2_idx]);
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dev_dbg(mmu_info->dev,
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"unmap l2 index %u with pteval 0x%10.10llx\n",
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l2_idx, TBL_PHYS_ADDR(l2_pt[l2_idx]));
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"unmap l2 index %u with pteval 0x%p\n",
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l2_idx, &pteval);
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l2_pt[l2_idx] = mmu_info->dummy_page_pteval;
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clflush_cache_range((void *)&l2_pt[l2_idx],
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@ -525,9 +530,10 @@ static struct ipu6_mmu_info *ipu6_mmu_alloc(struct ipu6_device *isp)
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return NULL;
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mmu_info->aperture_start = 0;
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mmu_info->aperture_end = DMA_BIT_MASK(isp->secure_mode ?
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IPU6_MMU_ADDR_BITS :
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IPU6_MMU_ADDR_BITS_NON_SECURE);
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mmu_info->aperture_end =
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(dma_addr_t)DMA_BIT_MASK(isp->secure_mode ?
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IPU6_MMU_ADDR_BITS :
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IPU6_MMU_ADDR_BITS_NON_SECURE);
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mmu_info->pgsize_bitmap = SZ_4K;
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mmu_info->dev = &isp->pdev->dev;
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