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HID: intel-thc-hid: intel-thc: Add THC I2C config interfaces
Add I2C bus related APIs to initialize I2C sub-system parameters, such as bus speed, slave address, address bit. As I2C sub-system hasn't auto register save and restore support, provide APIs to do it manually. Co-developed-by: Xinpeng Sun <xinpeng.sun@intel.com> Signed-off-by: Xinpeng Sun <xinpeng.sun@intel.com> Signed-off-by: Even Xu <even.xu@intel.com> Tested-by: Rui Zhang <rui1.zhang@intel.com> Tested-by: Mark Pearson <mpearson-lenovo@squebb.ca> Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Mark Pearson <mpearson-lenovo@squebb.ca> Tested-by: Aaron Ma <aaron.ma@canonical.com> Signed-off-by: Jiri Kosina <jkosina@suse.com>
This commit is contained in:
Even Xu
Jiri Kosina
parent
f02bcabad0
commit
4228966def
@ -1290,6 +1290,287 @@ void thc_spi_input_output_address_config(struct thc_device *dev, u32 input_hdr_a
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}
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EXPORT_SYMBOL_NS_GPL(thc_spi_input_output_address_config, "INTEL_THC");
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static int thc_i2c_subip_pio_read(struct thc_device *dev, const u32 address,
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u32 *size, u32 *buffer)
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{
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int ret;
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if (!size || *size == 0 || !buffer) {
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dev_err(dev->dev, "Invalid input parameters, size %p, buffer %p\n",
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size, buffer);
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return -EINVAL;
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}
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if (mutex_lock_interruptible(&dev->thc_bus_lock))
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return -EINTR;
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ret = prepare_pio(dev, THC_PIO_OP_I2C_SUBSYSTEM_READ, address, *size);
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if (ret < 0)
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goto end;
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pio_start(dev, 0, NULL);
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ret = pio_wait(dev);
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if (ret < 0)
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goto end;
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ret = pio_complete(dev, buffer, size);
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if (ret < 0)
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goto end;
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end:
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mutex_unlock(&dev->thc_bus_lock);
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if (ret)
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dev_err_once(dev->dev, "Read THC I2C SubIP register failed %d, offset %u\n",
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ret, address);
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return ret;
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}
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static int thc_i2c_subip_pio_write(struct thc_device *dev, const u32 address,
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const u32 size, const u32 *buffer)
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{
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int ret;
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if (size == 0 || !buffer) {
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dev_err(dev->dev, "Invalid input parameters, size %u, buffer %p\n",
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size, buffer);
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return -EINVAL;
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}
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if (mutex_lock_interruptible(&dev->thc_bus_lock))
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return -EINTR;
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ret = prepare_pio(dev, THC_PIO_OP_I2C_SUBSYSTEM_WRITE, address, size);
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if (ret < 0)
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goto end;
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pio_start(dev, size, buffer);
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ret = pio_wait(dev);
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if (ret < 0)
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goto end;
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ret = pio_complete(dev, NULL, NULL);
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if (ret < 0)
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goto end;
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end:
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mutex_unlock(&dev->thc_bus_lock);
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if (ret)
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dev_err_once(dev->dev, "Write THC I2C SubIP register failed %d, offset %u\n",
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ret, address);
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return ret;
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}
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#define I2C_SUBIP_CON_DEFAULT 0x663
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#define I2C_SUBIP_INT_MASK_DEFAULT 0x7FFF
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#define I2C_SUBIP_RX_TL_DEFAULT 62
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#define I2C_SUBIP_TX_TL_DEFAULT 0
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#define I2C_SUBIP_DMA_TDLR_DEFAULT 7
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#define I2C_SUBIP_DMA_RDLR_DEFAULT 7
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static int thc_i2c_subip_set_speed(struct thc_device *dev, const u32 speed,
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const u32 hcnt, const u32 lcnt)
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{
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u32 hcnt_offset, lcnt_offset;
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u32 val;
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int ret;
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switch (speed) {
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case THC_I2C_STANDARD:
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hcnt_offset = THC_I2C_IC_SS_SCL_HCNT_OFFSET;
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lcnt_offset = THC_I2C_IC_SS_SCL_LCNT_OFFSET;
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break;
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case THC_I2C_FAST_AND_PLUS:
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hcnt_offset = THC_I2C_IC_FS_SCL_HCNT_OFFSET;
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lcnt_offset = THC_I2C_IC_FS_SCL_LCNT_OFFSET;
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break;
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case THC_I2C_HIGH_SPEED:
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hcnt_offset = THC_I2C_IC_HS_SCL_HCNT_OFFSET;
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lcnt_offset = THC_I2C_IC_HS_SCL_LCNT_OFFSET;
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break;
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default:
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dev_err_once(dev->dev, "Unsupported i2c speed %d\n", speed);
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ret = -EINVAL;
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return ret;
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}
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ret = thc_i2c_subip_pio_write(dev, hcnt_offset, sizeof(u32), &hcnt);
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if (ret < 0)
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return ret;
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ret = thc_i2c_subip_pio_write(dev, lcnt_offset, sizeof(u32), &lcnt);
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if (ret < 0)
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return ret;
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val = I2C_SUBIP_CON_DEFAULT & ~THC_I2C_IC_CON_SPEED;
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val |= FIELD_PREP(THC_I2C_IC_CON_SPEED, speed);
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_CON_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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return 0;
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}
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static u32 i2c_subip_regs[] = {
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THC_I2C_IC_CON_OFFSET,
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THC_I2C_IC_TAR_OFFSET,
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THC_I2C_IC_INTR_MASK_OFFSET,
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THC_I2C_IC_RX_TL_OFFSET,
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THC_I2C_IC_TX_TL_OFFSET,
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THC_I2C_IC_DMA_CR_OFFSET,
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THC_I2C_IC_DMA_TDLR_OFFSET,
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THC_I2C_IC_DMA_RDLR_OFFSET,
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THC_I2C_IC_SS_SCL_HCNT_OFFSET,
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THC_I2C_IC_SS_SCL_LCNT_OFFSET,
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THC_I2C_IC_FS_SCL_HCNT_OFFSET,
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THC_I2C_IC_FS_SCL_LCNT_OFFSET,
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THC_I2C_IC_HS_SCL_HCNT_OFFSET,
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THC_I2C_IC_HS_SCL_LCNT_OFFSET,
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THC_I2C_IC_ENABLE_OFFSET,
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};
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/**
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* thc_i2c_subip_init - Initialize and configure THC I2C subsystem
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*
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* @dev: The pointer of THC private device context
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* @target_address: Slave address of touch device (TIC)
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* @speed: I2C bus frequency speed mode
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* @hcnt: I2C clock SCL high count
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* @lcnt: I2C clock SCL low count
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*
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* Return: 0 on success, other error codes on failed.
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*/
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int thc_i2c_subip_init(struct thc_device *dev, const u32 target_address,
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const u32 speed, const u32 hcnt, const u32 lcnt)
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{
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u32 read_size = sizeof(u32);
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u32 val;
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int ret;
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ret = thc_i2c_subip_pio_read(dev, THC_I2C_IC_ENABLE_OFFSET, &read_size, &val);
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if (ret < 0)
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return ret;
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val &= ~THC_I2C_IC_ENABLE_ENABLE;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_ENABLE_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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ret = thc_i2c_subip_pio_read(dev, THC_I2C_IC_TAR_OFFSET, &read_size, &val);
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if (ret < 0)
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return ret;
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val &= ~THC_I2C_IC_TAR_IC_TAR;
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val |= FIELD_PREP(THC_I2C_IC_TAR_IC_TAR, target_address);
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_TAR_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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ret = thc_i2c_subip_set_speed(dev, speed, hcnt, lcnt);
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if (ret < 0)
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return ret;
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val = I2C_SUBIP_INT_MASK_DEFAULT;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_INTR_MASK_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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val = I2C_SUBIP_RX_TL_DEFAULT;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_RX_TL_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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val = I2C_SUBIP_TX_TL_DEFAULT;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_TX_TL_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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val = THC_I2C_IC_DMA_CR_RDMAE | THC_I2C_IC_DMA_CR_TDMAE;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_DMA_CR_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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val = I2C_SUBIP_DMA_TDLR_DEFAULT;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_DMA_TDLR_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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val = I2C_SUBIP_DMA_RDLR_DEFAULT;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_DMA_RDLR_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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ret = thc_i2c_subip_pio_read(dev, THC_I2C_IC_ENABLE_OFFSET, &read_size, &val);
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if (ret < 0)
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return ret;
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val |= THC_I2C_IC_ENABLE_ENABLE;
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ret = thc_i2c_subip_pio_write(dev, THC_I2C_IC_ENABLE_OFFSET, sizeof(u32), &val);
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if (ret < 0)
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return ret;
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dev->i2c_subip_regs = devm_kzalloc(dev->dev, sizeof(i2c_subip_regs), GFP_KERNEL);
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if (!dev->i2c_subip_regs)
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return PTR_ERR(dev->i2c_subip_regs);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(thc_i2c_subip_init, "INTEL_THC");
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/**
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* thc_i2c_subip_regs_save - Save THC I2C sub-subsystem register values to THC device context
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*
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* @dev: The pointer of THC private device context
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*
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* Return: 0 on success, other error codes on failed.
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*/
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int thc_i2c_subip_regs_save(struct thc_device *dev)
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{
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int ret;
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u32 read_size = sizeof(u32);
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for (int i = 0; i < ARRAY_SIZE(i2c_subip_regs); i++) {
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ret = thc_i2c_subip_pio_read(dev, i2c_subip_regs[i],
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&read_size, (u32 *)&dev->i2c_subip_regs + i);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(thc_i2c_subip_regs_save, "INTEL_THC");
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/**
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* thc_i2c_subip_regs_restore - Restore THC I2C subsystem registers from THC device context
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*
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* @dev: The pointer of THC private device context
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*
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* Return: 0 on success, other error codes on failed.
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*/
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int thc_i2c_subip_regs_restore(struct thc_device *dev)
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{
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int ret;
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u32 write_size = sizeof(u32);
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for (int i = 0; i < ARRAY_SIZE(i2c_subip_regs); i++) {
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ret = thc_i2c_subip_pio_write(dev, i2c_subip_regs[i],
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write_size, (u32 *)&dev->i2c_subip_regs + i);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(thc_i2c_subip_regs_restore, "INTEL_THC");
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MODULE_AUTHOR("Xinpeng Sun <xinpeng.sun@intel.com>");
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MODULE_AUTHOR("Even Xu <even.xu@intel.com>");
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@ -61,6 +61,7 @@ enum thc_int_type {
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* @write_done: bool value that indicates if DMA write is done
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* @swdma_done: bool value that indicates if SWDMA swquence is done
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* @perf_limit: the delay between read operation and write operation
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* @i2c_subip_regs: the copy of THC I2C sub-system registers for resuming restore
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*/
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struct thc_device {
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struct device *dev;
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@ -78,6 +79,8 @@ struct thc_device {
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bool swdma_done;
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u32 perf_limit;
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u32 *i2c_subip_regs;
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};
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struct thc_device *thc_dev_init(struct device *device, void __iomem *mem_addr);
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@ -105,5 +108,9 @@ int thc_spi_write_config(struct thc_device *dev, u32 spi_freq_val,
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u32 io_mode, u32 opcode, u32 spi_wr_mps, u32 perf_limit);
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void thc_spi_input_output_address_config(struct thc_device *dev, u32 input_hdr_addr,
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u32 input_bdy_addr, u32 output_addr);
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int thc_i2c_subip_init(struct thc_device *dev, const u32 target_address,
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const u32 speed, const u32 hcnt, const u32 lcnt);
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int thc_i2c_subip_regs_save(struct thc_device *dev);
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int thc_i2c_subip_regs_restore(struct thc_device *dev);
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#endif /* _INTEL_THC_DEV_H_ */
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@ -749,4 +749,133 @@ enum thc_spi_frq_div {
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THC_SPI_FRQ_DIV_7 = 7,
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};
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/* THC I2C sub-system registers */
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#define THC_I2C_IC_CON_OFFSET 0x0
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#define THC_I2C_IC_TAR_OFFSET 0x4
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#define THC_I2C_IC_SAR_OFFSET 0x8
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#define THC_I2C_IC_HS_MADDR_OFFSET 0xC
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#define THC_I2C_IC_DATA_CMD_OFFSET 0x10
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#define THC_I2C_IC_SS_SCL_HCNT_OFFSET 0x14
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#define THC_I2C_IC_UFM_SCL_HCNT_OFFSET 0x14
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#define THC_I2C_IC_SS_SCL_LCNT_OFFSET 0x18
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#define THC_I2C_IC_UFM_SCL_LCNT_OFFSET 0x18
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#define THC_I2C_IC_FS_SCL_HCNT_OFFSET 0x1C
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#define THC_I2C_IC_UFM_TBUF_CNT_OFFSET 0x1C
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#define THC_I2C_IC_FS_SCL_LCNT_OFFSET 0x20
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#define THC_I2C_IC_HS_SCL_HCNT_OFFSET 0x24
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#define THC_I2C_IC_HS_SCL_LCNT_OFFSET 0x28
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#define THC_I2C_IC_INTR_STAT_OFFSET 0x2C
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#define THC_I2C_IC_INTR_MASK_OFFSET 0x30
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#define THC_I2C_IC_RAW_INTR_STAT_OFFSET 0x34
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#define THC_I2C_IC_RX_TL_OFFSET 0x38
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#define THC_I2C_IC_TX_TL_OFFSET 0x3C
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#define THC_I2C_IC_CLR_INTR_OFFSET 0x40
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#define THC_I2C_IC_CLR_RX_UNDER_OFFSET 0x44
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#define THC_I2C_IC_CLR_RX_OVER_OFFSET 0x48
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#define THC_I2C_IC_CLR_TX_OVER_OFFSET 0x4C
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#define THC_I2C_IC_CLR_RD_REQ_OFFSET 0x50
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#define THC_I2C_IC_CLR_TX_ABRT_OFFSET 0x54
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#define THC_I2C_IC_CLR_RX_DONE_OFFSET 0x58
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#define THC_I2C_IC_CLR_ACTIVITY_OFFSET 0x5C
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#define THC_I2C_IC_CLR_STOP_DET_OFFSET 0x60
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#define THC_I2C_IC_CLR_START_DET_OFFSET 0x64
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#define THC_I2C_IC_CLR_GEN_CALL_OFFSET 0x68
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#define THC_I2C_IC_ENABLE_OFFSET 0x6C
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#define THC_I2C_IC_STATUS_OFFSET 0x70
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#define THC_I2C_IC_TXFLR_OFFSET 0x74
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#define THC_I2C_IC_RXFLR_OFFSET 0x78
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#define THC_I2C_IC_SDA_HOLD_OFFSET 0x7C
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#define THC_I2C_IC_TX_ABRT_SOURCE_OFFSET 0x80
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#define THC_I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x84
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#define THC_I2C_IC_DMA_CR_OFFSET 0x88
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#define THC_I2C_IC_DMA_TDLR_OFFSET 0x8C
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#define THC_I2C_IC_DMA_RDLR_OFFSET 0x90
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#define THC_I2C_IC_SDA_SETUP_OFFSET 0x94
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#define THC_I2C_IC_ACK_GENERAL_CALL_OFFSET 0x98
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#define THC_I2C_IC_ENABLE_STATUS_OFFSET 0x9C
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#define THC_I2C_IC_FS_SPKLEN_OFFSET 0xA0
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#define THC_I2C_IC_UFM_SPKLEN_OFFSET 0xA0
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#define THC_I2C_IC_HS_SPKLEN_OFFSET 0xA4
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#define THC_I2C_IC_CLR_RESTART_DET_OFFSET 0xA8
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#define THC_I2C_IC_SCL_STUCK_AT_LOW_TIMEOUT_OFFSET 0xAC
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#define THC_I2C_IC_SDA_STUCK_AT_LOW_TIMEOUT_OFFSET 0xB0
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#define THC_I2C_IC_CLR_SCL_STUCK_DET_OFFSET 0xB4
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#define THC_I2C_IC_DEVICE_ID_OFFSET 0xB8
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#define THC_I2C_IC_SMBUS_CLK_LOW_SEXT_OFFSET 0xBC
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#define THC_I2C_IC_SMBUS_CLK_LOW_MEXT_OFFSET 0xC0
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#define THC_I2C_IC_SMBUS_THIGH_MAX_IDLE_COUNT_OFFSET 0xC4
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#define THC_I2C_IC_SMBUS_INTR_STAT_OFFSET 0xC8
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#define THC_I2C_IC_SMBUS_INTR_MASK_OFFSET 0xCC
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#define THC_I2C_IC_SMBUS_RAW_INTR_STAT_OFFSET 0xD0
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#define THC_I2C_IC_CLR_SMBUS_INTR_OFFSET 0xD4
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#define THC_I2C_IC_OPTIONAL_SAR_OFFSET 0xD8
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#define THC_I2C_IC_SMBUS_UDID_LSB_OFFSET 0xDC
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#define THC_I2C_IC_SMBUS_UDID_WORD0_OFFSET 0xDC
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#define THC_I2C_IC_SMBUS_UDID_WORD1_OFFSET 0xE0
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#define THC_I2C_IC_SMBUS_UDID_WORD2_OFFSET 0xE4
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#define THC_I2C_IC_SMBUS_UDID_WORD3_OFFSET 0xE8
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#define THC_I2C_IC_COMP_PARAM_1_OFFSET 0xF4
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#define THC_I2C_IC_COMP_VERSION_OFFSET 0xF8
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#define THC_I2C_IC_COMP_TYPE_OFFSET 0xFC
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/**
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* THC I2C sub-system supported speed mode
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*/
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enum THC_I2C_SPEED_MODE {
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THC_I2C_STANDARD = 1,
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THC_I2C_FAST_AND_PLUS = 2,
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THC_I2C_HIGH_SPEED = 3,
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};
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/* THC I2C sub-system register bits definition */
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#define THC_I2C_IC_ENABLE_ENABLE BIT(0)
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#define THC_I2C_IC_ENABLE_ABORT BIT(1)
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#define THC_I2C_IC_ENABLE_TX_CMD_BLOCK BIT(2)
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#define THC_I2C_IC_ENABLE_SDA_STUCK_RECOVERY_ENABLE BIT(3)
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#define THC_I2C_IC_ENABLE_SMBUS_CLK_RESET BIT(16)
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#define THC_I2C_IC_ENABLE_SMBUS_SUSPEND_EN BIT(17)
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#define THC_I2C_IC_ENABLE_SMBUS_ALERT_EN BIT(18)
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#define THC_I2C_IC_CON_MASTER_MODE BIT(0)
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#define THC_I2C_IC_CON_SPEED GENMASK(2, 1)
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#define THC_I2C_IC_CON_IC_10BITADDR_SLAVE BIT(3)
|
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#define THC_I2C_IC_CON_IC_10BITADDR_MASTER BIT(4)
|
||||
#define THC_I2C_IC_CON_IC_RESTART_EN BIT(5)
|
||||
#define THC_I2C_IC_CON_IC_SLAVE_DISABLE BIT(6)
|
||||
#define THC_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
|
||||
#define THC_I2C_IC_CON_TX_EMPTY_CTRL BIT(8)
|
||||
#define THC_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
|
||||
#define THC_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE BIT(10)
|
||||
#define THC_I2C_IC_CON_BUS_CLEAR_FEATURE_CTRL BIT(11)
|
||||
#define THC_I2C_IC_CON_OPTIONAL_SAR_CTRL BIT(16)
|
||||
#define THC_I2C_IC_CON_SMBUS_SLAVE_QUICK_EN BIT(17)
|
||||
#define THC_I2C_IC_CON_SMBUS_ARP_EN BIT(18)
|
||||
#define THC_I2C_IC_CON_SMBUS_PERSISTENT_SLV_ADDR_EN BIT(19)
|
||||
|
||||
#define THC_I2C_IC_TAR_IC_TAR GENMASK(9, 0)
|
||||
#define THC_I2C_IC_TAR_GC_OR_START BIT(10)
|
||||
#define THC_I2C_IC_TAR_SPECIAL BIT(11)
|
||||
#define THC_I2C_IC_TAR_IC_10BITADDR_MASTER BIT(12)
|
||||
#define THC_I2C_IC_TAR_DEVICE_ID BIT(13)
|
||||
#define THC_I2C_IC_TAR_SMBUS_QUICK_CMD BIT(16)
|
||||
|
||||
#define THC_I2C_IC_INTR_MASK_M_RX_UNDER BIT(0)
|
||||
#define THC_I2C_IC_INTR_MASK_M_RX_OVER BIT(1)
|
||||
#define THC_I2C_IC_INTR_MASK_M_RX_FULL BIT(2)
|
||||
#define THC_I2C_IC_INTR_MASK_M_TX_OVER BIT(3)
|
||||
#define THC_I2C_IC_INTR_MASK_M_TX_EMPTY BIT(4)
|
||||
#define THC_I2C_IC_INTR_MASK_M_RD_REQ BIT(5)
|
||||
#define THC_I2C_IC_INTR_MASK_M_TX_ABRT BIT(6)
|
||||
#define THC_I2C_IC_INTR_MASK_M_RX_DONE BIT(7)
|
||||
#define THC_I2C_IC_INTR_MASK_M_ACTIVITY BIT(8)
|
||||
#define THC_I2C_IC_INTR_MASK_M_STOP_DET BIT(9)
|
||||
#define THC_I2C_IC_INTR_MASK_M_START_DET BIT(10)
|
||||
#define THC_I2C_IC_INTR_MASK_M_GEN_CALL BIT(11)
|
||||
#define THC_I2C_IC_INTR_MASK_M_RESTART_DET BIT(12)
|
||||
#define THC_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD BIT(13)
|
||||
#define THC_I2C_IC_INTR_MASK_M_SCL_STUCK_AT_LOW BIT(14)
|
||||
|
||||
#define THC_I2C_IC_DMA_CR_RDMAE BIT(0)
|
||||
#define THC_I2C_IC_DMA_CR_TDMAE BIT(1)
|
||||
|
||||
#endif /* _INTEL_THC_HW_H_ */
|
||||
|
||||
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