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i2c: spacemit: add support for SpacemiT K1 SoC
This patch introduces basic I2C support for the SpacemiT K1 SoC, utilizing interrupts for transfers. The driver has been tested using i2c-tools on a Bananapi-F3 board, and basic I2C read/write operations have been confirmed to work. Signed-off-by: Troy Mitchell <troymitchell988@gmail.com> Reviewed-by: Alex Elder <elder@riscstar.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20250319-k1-i2c-master-v8-2-013e2df2b78d@gmail.com
This commit is contained in:
Troy Mitchell
Andi Shyti
parent
76fe9ac17f
commit
5ea558473f
@ -783,6 +783,23 @@ config I2C_JZ4780
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If you don't know what to do here, say N.
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config I2C_K1
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tristate "SpacemiT K1 I2C adapter"
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depends on ARCH_SPACEMIT || COMPILE_TEST
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depends on OF
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help
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This option enables support for the I2C interface on the SpacemiT K1
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platform.
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If you enable this configuration, the kernel will include support for
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the I2C adapter specific to the SpacemiT K1 platform. This driver can
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be used to manage I2C bus transactions, which are necessary for
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interfacing with I2C peripherals such as sensors, EEPROMs, and other
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devices.
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This driver can also be built as a module. If so, the
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module will be called `i2c-k1`.
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config I2C_KEBA
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tristate "KEBA I2C controller support"
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depends on HAS_IOMEM
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@ -74,6 +74,7 @@ obj-$(CONFIG_I2C_IMX) += i2c-imx.o
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obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-lpi2c.o
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obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
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obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
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obj-$(CONFIG_I2C_K1) += i2c-k1.o
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obj-$(CONFIG_I2C_KEBA) += i2c-keba.o
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obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
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obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o
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602
drivers/i2c/busses/i2c-k1.c
Normal file
602
drivers/i2c/busses/i2c-k1.c
Normal file
@ -0,0 +1,602 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2024-2025 Troy Mitchell <troymitchell988@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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/* spacemit i2c registers */
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#define SPACEMIT_ICR 0x0 /* Control register */
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#define SPACEMIT_ISR 0x4 /* Status register */
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#define SPACEMIT_IDBR 0xc /* Data buffer register */
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#define SPACEMIT_IBMR 0x1c /* Bus monitor register */
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/* SPACEMIT_ICR register fields */
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#define SPACEMIT_CR_START BIT(0) /* start bit */
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#define SPACEMIT_CR_STOP BIT(1) /* stop bit */
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#define SPACEMIT_CR_ACKNAK BIT(2) /* send ACK(0) or NAK(1) */
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#define SPACEMIT_CR_TB BIT(3) /* transfer byte bit */
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/* Bits 4-7 are reserved */
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#define SPACEMIT_CR_MODE_FAST BIT(8) /* bus mode (master operation) */
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/* Bit 9 is reserved */
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#define SPACEMIT_CR_UR BIT(10) /* unit reset */
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/* Bits 11-12 are reserved */
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#define SPACEMIT_CR_SCLE BIT(13) /* master clock enable */
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#define SPACEMIT_CR_IUE BIT(14) /* unit enable */
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/* Bits 15-17 are reserved */
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#define SPACEMIT_CR_ALDIE BIT(18) /* enable arbitration interrupt */
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#define SPACEMIT_CR_DTEIE BIT(19) /* enable TX interrupts */
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#define SPACEMIT_CR_DRFIE BIT(20) /* enable RX interrupts */
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#define SPACEMIT_CR_GCD BIT(21) /* general call disable */
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#define SPACEMIT_CR_BEIE BIT(22) /* enable bus error ints */
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/* Bits 23-24 are reserved */
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#define SPACEMIT_CR_MSDIE BIT(25) /* master STOP detected int enable */
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#define SPACEMIT_CR_MSDE BIT(26) /* master STOP detected enable */
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#define SPACEMIT_CR_TXDONEIE BIT(27) /* transaction done int enable */
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#define SPACEMIT_CR_TXEIE BIT(28) /* transmit FIFO empty int enable */
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#define SPACEMIT_CR_RXHFIE BIT(29) /* receive FIFO half-full int enable */
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#define SPACEMIT_CR_RXFIE BIT(30) /* receive FIFO full int enable */
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#define SPACEMIT_CR_RXOVIE BIT(31) /* receive FIFO overrun int enable */
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#define SPACEMIT_I2C_INT_CTRL_MASK (SPACEMIT_CR_ALDIE | SPACEMIT_CR_DTEIE | \
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SPACEMIT_CR_DRFIE | SPACEMIT_CR_BEIE | \
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SPACEMIT_CR_TXDONEIE | SPACEMIT_CR_TXEIE | \
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SPACEMIT_CR_RXHFIE | SPACEMIT_CR_RXFIE | \
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SPACEMIT_CR_RXOVIE | SPACEMIT_CR_MSDIE)
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/* SPACEMIT_ISR register fields */
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/* Bits 0-13 are reserved */
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#define SPACEMIT_SR_ACKNAK BIT(14) /* ACK/NACK status */
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#define SPACEMIT_SR_UB BIT(15) /* unit busy */
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#define SPACEMIT_SR_IBB BIT(16) /* i2c bus busy */
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#define SPACEMIT_SR_EBB BIT(17) /* early bus busy */
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#define SPACEMIT_SR_ALD BIT(18) /* arbitration loss detected */
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#define SPACEMIT_SR_ITE BIT(19) /* TX buffer empty */
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#define SPACEMIT_SR_IRF BIT(20) /* RX buffer full */
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#define SPACEMIT_SR_GCAD BIT(21) /* general call address detected */
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#define SPACEMIT_SR_BED BIT(22) /* bus error no ACK/NAK */
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#define SPACEMIT_SR_SAD BIT(23) /* slave address detected */
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#define SPACEMIT_SR_SSD BIT(24) /* slave stop detected */
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/* Bit 25 is reserved */
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#define SPACEMIT_SR_MSD BIT(26) /* master stop detected */
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#define SPACEMIT_SR_TXDONE BIT(27) /* transaction done */
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#define SPACEMIT_SR_TXE BIT(28) /* TX FIFO empty */
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#define SPACEMIT_SR_RXHF BIT(29) /* RX FIFO half-full */
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#define SPACEMIT_SR_RXF BIT(30) /* RX FIFO full */
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#define SPACEMIT_SR_RXOV BIT(31) /* RX FIFO overrun */
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#define SPACEMIT_I2C_INT_STATUS_MASK (SPACEMIT_SR_RXOV | SPACEMIT_SR_RXF | SPACEMIT_SR_RXHF | \
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SPACEMIT_SR_TXE | SPACEMIT_SR_TXDONE | SPACEMIT_SR_MSD | \
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SPACEMIT_SR_SSD | SPACEMIT_SR_SAD | SPACEMIT_SR_BED | \
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SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \
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SPACEMIT_SR_ALD)
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/* SPACEMIT_IBMR register fields */
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#define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */
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#define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */
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/* i2c bus recover timeout: us */
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#define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000
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#define SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ 100000 /* Hz */
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#define SPACEMIT_I2C_MAX_FAST_MODE_FREQ 400000 /* Hz */
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#define SPACEMIT_SR_ERR (SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_ALD)
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enum spacemit_i2c_state {
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SPACEMIT_STATE_IDLE,
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SPACEMIT_STATE_START,
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SPACEMIT_STATE_READ,
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SPACEMIT_STATE_WRITE,
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};
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/* i2c-spacemit driver's main struct */
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struct spacemit_i2c_dev {
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struct device *dev;
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struct i2c_adapter adapt;
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/* hardware resources */
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void __iomem *base;
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int irq;
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u32 clock_freq;
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struct i2c_msg *msgs;
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u32 msg_num;
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/* index of the current message being processed */
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u32 msg_idx;
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u8 *msg_buf;
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/* the number of unprocessed bytes remaining in the current message */
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u32 unprocessed;
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enum spacemit_i2c_state state;
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bool read;
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struct completion complete;
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u32 status;
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};
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static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c)
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{
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u32 val;
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val = readl(i2c->base + SPACEMIT_ICR);
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val |= SPACEMIT_CR_IUE;
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writel(val, i2c->base + SPACEMIT_ICR);
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}
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static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c)
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{
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u32 val;
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val = readl(i2c->base + SPACEMIT_ICR);
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val &= ~SPACEMIT_CR_IUE;
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writel(val, i2c->base + SPACEMIT_ICR);
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}
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static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c)
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{
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writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR);
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udelay(5);
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writel(0, i2c->base + SPACEMIT_ICR);
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}
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static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c)
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{
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dev_dbg(i2c->dev, "i2c error status: 0x%08x\n", i2c->status);
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if (i2c->status & (SPACEMIT_SR_BED | SPACEMIT_SR_ALD)) {
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spacemit_i2c_reset(i2c);
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return -EAGAIN;
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}
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return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO;
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}
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static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c)
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{
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u32 status;
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/* if bus is locked, reset unit. 0: locked */
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status = readl(i2c->base + SPACEMIT_IBMR);
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if ((status & SPACEMIT_BMR_SDA) && (status & SPACEMIT_BMR_SCL))
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return;
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spacemit_i2c_reset(i2c);
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usleep_range(10, 20);
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/* check scl status again */
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status = readl(i2c->base + SPACEMIT_IBMR);
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if (!(status & SPACEMIT_BMR_SCL))
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dev_warn_ratelimited(i2c->dev, "unit reset failed\n");
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}
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static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c)
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{
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int ret;
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u32 val;
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val = readl(i2c->base + SPACEMIT_ISR);
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if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)))
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return 0;
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ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR,
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val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)),
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1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT);
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if (ret)
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spacemit_i2c_reset(i2c);
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return ret;
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}
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static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c)
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{
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/* in case bus is not released after transfer completes */
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if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) {
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spacemit_i2c_conditionally_reset_bus(i2c);
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usleep_range(90, 150);
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}
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}
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static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c)
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{
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u32 val;
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/*
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* Unmask interrupt bits for all xfer mode:
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* bus error, arbitration loss detected.
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* For transaction complete signal, we use master stop
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* interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE.
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*/
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val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE;
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/*
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* Unmask interrupt bits for interrupt xfer mode:
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* When IDBR receives a byte, an interrupt is triggered.
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*
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* For the tx empty interrupt, it will be enabled in the
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* i2c_start function.
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* Otherwise, it will cause an erroneous empty interrupt before i2c_start.
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*/
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val |= SPACEMIT_CR_DRFIE;
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if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ)
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val |= SPACEMIT_CR_MODE_FAST;
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/* disable response to general call */
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val |= SPACEMIT_CR_GCD;
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/* enable SCL clock output */
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val |= SPACEMIT_CR_SCLE;
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/* enable master stop detected */
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val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE;
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writel(val, i2c->base + SPACEMIT_ICR);
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}
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static inline void
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spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask)
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{
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writel(mask & SPACEMIT_I2C_INT_STATUS_MASK, i2c->base + SPACEMIT_ISR);
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}
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static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c)
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{
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u32 target_addr_rw, val;
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struct i2c_msg *cur_msg = i2c->msgs + i2c->msg_idx;
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i2c->read = !!(cur_msg->flags & I2C_M_RD);
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i2c->state = SPACEMIT_STATE_START;
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target_addr_rw = (cur_msg->addr & 0x7f) << 1;
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if (cur_msg->flags & I2C_M_RD)
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target_addr_rw |= 1;
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writel(target_addr_rw, i2c->base + SPACEMIT_IDBR);
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/* send start pulse */
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val = readl(i2c->base + SPACEMIT_ICR);
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val &= ~SPACEMIT_CR_STOP;
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val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE;
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writel(val, i2c->base + SPACEMIT_ICR);
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}
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static void spacemit_i2c_stop(struct spacemit_i2c_dev *i2c)
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{
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u32 val;
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val = readl(i2c->base + SPACEMIT_ICR);
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val |= SPACEMIT_CR_STOP | SPACEMIT_CR_ALDIE | SPACEMIT_CR_TB;
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if (i2c->read)
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val |= SPACEMIT_CR_ACKNAK;
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writel(val, i2c->base + SPACEMIT_ICR);
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}
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static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c)
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{
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unsigned long time_left;
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struct i2c_msg *msg;
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for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) {
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msg = &i2c->msgs[i2c->msg_idx];
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i2c->msg_buf = msg->buf;
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i2c->unprocessed = msg->len;
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i2c->status = 0;
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reinit_completion(&i2c->complete);
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spacemit_i2c_start(i2c);
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time_left = wait_for_completion_timeout(&i2c->complete,
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i2c->adapt.timeout);
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if (!time_left) {
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dev_err(i2c->dev, "msg completion timeout\n");
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spacemit_i2c_conditionally_reset_bus(i2c);
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spacemit_i2c_reset(i2c);
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return -ETIMEDOUT;
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}
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if (i2c->status & SPACEMIT_SR_ERR)
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return spacemit_i2c_handle_err(i2c);
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}
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return 0;
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}
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static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c)
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{
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if (i2c->msg_idx != i2c->msg_num - 1)
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return false;
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if (i2c->read)
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return i2c->unprocessed == 1;
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return !i2c->unprocessed;
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}
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static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c)
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{
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/* if transfer completes, SPACEMIT_ISR will handle it */
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if (i2c->status & SPACEMIT_SR_MSD)
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return;
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if (i2c->unprocessed) {
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writel(*i2c->msg_buf++, i2c->base + SPACEMIT_IDBR);
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i2c->unprocessed--;
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return;
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}
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/* SPACEMIT_STATE_IDLE avoids trigger next byte */
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i2c->state = SPACEMIT_STATE_IDLE;
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complete(&i2c->complete);
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}
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static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c)
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{
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if (i2c->unprocessed) {
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*i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR);
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i2c->unprocessed--;
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}
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/* if transfer completes, SPACEMIT_ISR will handle it */
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if (i2c->status & (SPACEMIT_SR_MSD | SPACEMIT_SR_ACKNAK))
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return;
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/* it has to append stop bit in icr that read last byte */
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if (i2c->unprocessed)
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return;
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/* SPACEMIT_STATE_IDLE avoids trigger next byte */
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i2c->state = SPACEMIT_STATE_IDLE;
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complete(&i2c->complete);
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}
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static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c)
|
||||
{
|
||||
i2c->state = i2c->read ? SPACEMIT_STATE_READ : SPACEMIT_STATE_WRITE;
|
||||
if (i2c->state == SPACEMIT_STATE_WRITE)
|
||||
spacemit_i2c_handle_write(i2c);
|
||||
}
|
||||
|
||||
static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Send transaction complete signal:
|
||||
* error happens, detect master stop
|
||||
*/
|
||||
if (!(i2c->status & (SPACEMIT_SR_ERR | SPACEMIT_SR_MSD)))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Here the transaction is already done, we don't need any
|
||||
* other interrupt signals from now, in case any interrupt
|
||||
* happens before spacemit_i2c_xfer to disable irq and i2c unit,
|
||||
* we mask all the interrupt signals and clear the interrupt
|
||||
* status.
|
||||
*/
|
||||
val = readl(i2c->base + SPACEMIT_ICR);
|
||||
val &= ~SPACEMIT_I2C_INT_CTRL_MASK;
|
||||
writel(val, i2c->base + SPACEMIT_ICR);
|
||||
|
||||
spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK);
|
||||
|
||||
i2c->state = SPACEMIT_STATE_IDLE;
|
||||
complete(&i2c->complete);
|
||||
}
|
||||
|
||||
static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid)
|
||||
{
|
||||
struct spacemit_i2c_dev *i2c = devid;
|
||||
u32 status, val;
|
||||
|
||||
status = readl(i2c->base + SPACEMIT_ISR);
|
||||
if (!status)
|
||||
return IRQ_HANDLED;
|
||||
|
||||
i2c->status = status;
|
||||
|
||||
spacemit_i2c_clear_int_status(i2c, status);
|
||||
|
||||
if (i2c->status & SPACEMIT_SR_ERR)
|
||||
goto err_out;
|
||||
|
||||
val = readl(i2c->base + SPACEMIT_ICR);
|
||||
val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START);
|
||||
writel(val, i2c->base + SPACEMIT_ICR);
|
||||
|
||||
switch (i2c->state) {
|
||||
case SPACEMIT_STATE_START:
|
||||
spacemit_i2c_handle_start(i2c);
|
||||
break;
|
||||
case SPACEMIT_STATE_READ:
|
||||
spacemit_i2c_handle_read(i2c);
|
||||
break;
|
||||
case SPACEMIT_STATE_WRITE:
|
||||
spacemit_i2c_handle_write(i2c);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (i2c->state != SPACEMIT_STATE_IDLE) {
|
||||
if (spacemit_i2c_is_last_msg(i2c)) {
|
||||
/* trigger next byte with stop */
|
||||
spacemit_i2c_stop(i2c);
|
||||
} else {
|
||||
/* trigger next byte */
|
||||
val |= SPACEMIT_CR_ALDIE | SPACEMIT_CR_TB;
|
||||
writel(val, i2c->base + SPACEMIT_ICR);
|
||||
}
|
||||
}
|
||||
|
||||
err_out:
|
||||
spacemit_i2c_err_check(i2c);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c)
|
||||
{
|
||||
unsigned long timeout;
|
||||
int idx = 0, cnt = 0;
|
||||
|
||||
for (; idx < i2c->msg_num; idx++)
|
||||
cnt += (i2c->msgs + idx)->len + 1;
|
||||
|
||||
/*
|
||||
* Multiply by 9 because each byte in I2C transmission requires
|
||||
* 9 clock cycles: 8 bits of data plus 1 ACK/NACK bit.
|
||||
*/
|
||||
timeout = cnt * 9 * USEC_PER_SEC / i2c->clock_freq;
|
||||
|
||||
i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num;
|
||||
}
|
||||
|
||||
static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num)
|
||||
{
|
||||
struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt);
|
||||
int ret;
|
||||
|
||||
i2c->msgs = msgs;
|
||||
i2c->msg_num = num;
|
||||
|
||||
spacemit_i2c_calc_timeout(i2c);
|
||||
|
||||
spacemit_i2c_init(i2c);
|
||||
|
||||
spacemit_i2c_enable(i2c);
|
||||
|
||||
ret = spacemit_i2c_wait_bus_idle(i2c);
|
||||
if (!ret)
|
||||
spacemit_i2c_xfer_msg(i2c);
|
||||
else if (ret < 0)
|
||||
dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret);
|
||||
else
|
||||
spacemit_i2c_check_bus_release(i2c);
|
||||
|
||||
spacemit_i2c_disable(i2c);
|
||||
|
||||
if (ret == -ETIMEDOUT || ret == -EAGAIN)
|
||||
dev_err(i2c->dev, "i2c transfer failed, ret %d err 0x%lx\n",
|
||||
ret, i2c->status & SPACEMIT_SR_ERR);
|
||||
|
||||
return ret < 0 ? ret : num;
|
||||
}
|
||||
|
||||
static u32 spacemit_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm spacemit_i2c_algo = {
|
||||
.xfer = spacemit_i2c_xfer,
|
||||
.functionality = spacemit_i2c_func,
|
||||
};
|
||||
|
||||
static int spacemit_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *of_node = pdev->dev.of_node;
|
||||
struct spacemit_i2c_dev *i2c;
|
||||
int ret;
|
||||
|
||||
i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
|
||||
if (!i2c)
|
||||
return -ENOMEM;
|
||||
|
||||
of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq);
|
||||
if (ret && ret != -EINVAL)
|
||||
dev_warn(dev, "failed to read clock-frequency property: %d\n", ret);
|
||||
|
||||
/* For now, this driver doesn't support high-speed. */
|
||||
if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) {
|
||||
dev_warn(dev, "unsupported clock frequency %u; using %u\n",
|
||||
i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ);
|
||||
i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ;
|
||||
} else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) {
|
||||
dev_warn(dev, "unsupported clock frequency %u; using %u\n",
|
||||
i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ);
|
||||
i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ;
|
||||
}
|
||||
|
||||
i2c->dev = &pdev->dev;
|
||||
|
||||
i2c->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(i2c->base))
|
||||
return dev_err_probe(dev, PTR_ERR(i2c->base), "failed to do ioremap");
|
||||
|
||||
i2c->irq = platform_get_irq(pdev, 0);
|
||||
if (i2c->irq < 0)
|
||||
return dev_err_probe(dev, i2c->irq, "failed to get irq resource");
|
||||
|
||||
ret = devm_request_irq(i2c->dev, i2c->irq, spacemit_i2c_irq_handler,
|
||||
IRQF_NO_SUSPEND | IRQF_ONESHOT, dev_name(i2c->dev), i2c);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to request irq");
|
||||
|
||||
clk = devm_clk_get_enabled(dev, "func");
|
||||
if (IS_ERR(clk))
|
||||
return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock");
|
||||
|
||||
clk = devm_clk_get_enabled(dev, "bus");
|
||||
if (IS_ERR(clk))
|
||||
return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock");
|
||||
|
||||
spacemit_i2c_reset(i2c);
|
||||
|
||||
i2c_set_adapdata(&i2c->adapt, i2c);
|
||||
i2c->adapt.owner = THIS_MODULE;
|
||||
i2c->adapt.algo = &spacemit_i2c_algo;
|
||||
i2c->adapt.dev.parent = i2c->dev;
|
||||
i2c->adapt.nr = pdev->id;
|
||||
|
||||
i2c->adapt.dev.of_node = of_node;
|
||||
|
||||
strscpy(i2c->adapt.name, "spacemit-i2c-adapter", sizeof(i2c->adapt.name));
|
||||
|
||||
init_completion(&i2c->complete);
|
||||
|
||||
platform_set_drvdata(pdev, i2c);
|
||||
|
||||
ret = i2c_add_numbered_adapter(&i2c->adapt);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret, "failed to add i2c adapter");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spacemit_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spacemit_i2c_dev *i2c = platform_get_drvdata(pdev);
|
||||
|
||||
i2c_del_adapter(&i2c->adapt);
|
||||
}
|
||||
|
||||
static const struct of_device_id spacemit_i2c_of_match[] = {
|
||||
{ .compatible = "spacemit,k1-i2c", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spacemit_i2c_of_match);
|
||||
|
||||
static struct platform_driver spacemit_i2c_driver = {
|
||||
.probe = spacemit_i2c_probe,
|
||||
.remove = spacemit_i2c_remove,
|
||||
.driver = {
|
||||
.name = "i2c-k1",
|
||||
.of_match_table = spacemit_i2c_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(spacemit_i2c_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("I2C bus driver for SpacemiT K1 SoC");
|
||||
Loading…
x
Reference in New Issue
Block a user