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rtc: pm8xxx: add support for uefi offset
On many Qualcomm platforms the PMIC RTC control and time registers are
read-only so that the RTC time can not be updated. Instead an offset
needs be stored in some machine-specific non-volatile memory, which the
driver can take into account.
Add support for storing a 32-bit offset from the GPS time epoch in a
UEFI variable so that the RTC time can be set on such platforms.
The UEFI variable is
882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo
and holds a 12-byte structure where the first four bytes is a GPS time
offset in little-endian byte order.
Note that this format is not arbitrary as the variable is shared with
the UEFI firmware (and Windows).
Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Tested-by: Steev Klimaszewski <steev@kali.org>
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Sebastian Reichel <sre@kernel.org> # Lenovo T14s Gen6
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250219134118.31017-3-johan+linaro@kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Johan Hovold
Alexandre Belloni
parent
931a88914a
commit
bba38b8748
@ -5,6 +5,7 @@
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <linux/efi.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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@ -16,9 +17,10 @@
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/unaligned.h>
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#include <asm/byteorder.h>
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/* RTC_CTRL register bit fields */
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#define PM8xxx_RTC_ENABLE BIT(7)
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#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
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@ -46,14 +48,21 @@ struct pm8xxx_rtc_regs {
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unsigned int alarm_en;
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};
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struct qcom_uefi_rtc_info {
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__le32 offset_gps;
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u8 reserved[8];
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} __packed;
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/**
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* struct pm8xxx_rtc - RTC driver internal structure
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* @rtc: RTC device
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* @regmap: regmap used to access registers
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* @allow_set_time: whether the time can be set
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* @use_uefi: use UEFI variable as fallback for offset
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* @alarm_irq: alarm irq number
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* @regs: register description
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* @dev: device structure
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* @rtc_info: qcom uefi rtc-info structure
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* @nvmem_cell: nvmem cell for offset
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* @offset: offset from epoch in seconds
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*/
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@ -61,13 +70,101 @@ struct pm8xxx_rtc {
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struct rtc_device *rtc;
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struct regmap *regmap;
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bool allow_set_time;
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bool use_uefi;
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int alarm_irq;
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const struct pm8xxx_rtc_regs *regs;
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struct device *dev;
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struct qcom_uefi_rtc_info rtc_info;
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struct nvmem_cell *nvmem_cell;
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u32 offset;
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};
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#ifdef CONFIG_EFI
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MODULE_IMPORT_NS("EFIVAR");
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#define QCOM_UEFI_NAME L"RTCInfo"
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#define QCOM_UEFI_GUID EFI_GUID(0x882f8c2b, 0x9646, 0x435f, \
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0x8d, 0xe5, 0xf2, 0x08, 0xff, 0x80, 0xc1, 0xbd)
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#define QCOM_UEFI_ATTRS (EFI_VARIABLE_NON_VOLATILE | \
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EFI_VARIABLE_BOOTSERVICE_ACCESS | \
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EFI_VARIABLE_RUNTIME_ACCESS)
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static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd)
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{
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struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info;
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unsigned long size = sizeof(*rtc_info);
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struct device *dev = rtc_dd->dev;
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efi_status_t status;
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u32 offset_gps;
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int rc;
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rc = efivar_lock();
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if (rc)
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return rc;
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status = efivar_get_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID, NULL,
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&size, rtc_info);
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efivar_unlock();
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if (status != EFI_SUCCESS) {
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dev_dbg(dev, "failed to read UEFI offset: %lu\n", status);
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return efi_status_to_err(status);
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}
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if (size != sizeof(*rtc_info)) {
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dev_dbg(dev, "unexpected UEFI structure size %lu\n", size);
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return -EINVAL;
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}
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dev_dbg(dev, "uefi_rtc_info = %*ph\n", (int)size, rtc_info);
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/* Convert from GPS to Unix time offset */
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offset_gps = le32_to_cpu(rtc_info->offset_gps);
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rtc_dd->offset = offset_gps + (u32)RTC_TIMESTAMP_EPOCH_GPS;
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return 0;
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}
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static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
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{
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struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info;
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unsigned long size = sizeof(*rtc_info);
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struct device *dev = rtc_dd->dev;
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efi_status_t status;
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u32 offset_gps;
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/* Convert from Unix to GPS time offset */
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offset_gps = offset - (u32)RTC_TIMESTAMP_EPOCH_GPS;
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rtc_info->offset_gps = cpu_to_le32(offset_gps);
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dev_dbg(dev, "efi_rtc_info = %*ph\n", (int)size, rtc_info);
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status = efivar_set_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID,
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QCOM_UEFI_ATTRS, size, rtc_info);
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if (status != EFI_SUCCESS) {
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dev_dbg(dev, "failed to write UEFI offset: %lx\n", status);
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return efi_status_to_err(status);
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}
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return 0;
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}
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#else /* CONFIG_EFI */
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static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd)
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{
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return -ENODEV;
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}
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static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_EFI */
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static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd)
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{
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size_t len;
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@ -110,14 +207,6 @@ static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
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return 0;
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}
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static int pm8xxx_rtc_read_offset(struct pm8xxx_rtc *rtc_dd)
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{
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if (!rtc_dd->nvmem_cell)
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return 0;
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return pm8xxx_rtc_read_nvmem_offset(rtc_dd);
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}
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static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
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{
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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@ -155,7 +244,7 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs)
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u32 offset;
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int rc;
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if (!rtc_dd->nvmem_cell)
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if (!rtc_dd->nvmem_cell && !rtc_dd->use_uefi)
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return -ENODEV;
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rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs);
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@ -167,7 +256,11 @@ static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs)
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if (offset == rtc_dd->offset)
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return 0;
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rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);
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if (rtc_dd->nvmem_cell)
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rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);
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else
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rc = pm8xxx_rtc_write_uefi_offset(rtc_dd, offset);
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if (rc)
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return rc;
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@ -455,6 +548,30 @@ static const struct of_device_id pm8xxx_id_table[] = {
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};
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MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
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static int pm8xxx_rtc_probe_offset(struct pm8xxx_rtc *rtc_dd)
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{
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int rc;
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rtc_dd->nvmem_cell = devm_nvmem_cell_get(rtc_dd->dev, "offset");
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if (IS_ERR(rtc_dd->nvmem_cell)) {
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rc = PTR_ERR(rtc_dd->nvmem_cell);
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if (rc != -ENOENT)
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return rc;
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rtc_dd->nvmem_cell = NULL;
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} else {
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return pm8xxx_rtc_read_nvmem_offset(rtc_dd);
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}
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/* Use UEFI storage as fallback if available */
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if (efivar_is_available()) {
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rc = pm8xxx_rtc_read_uefi_offset(rtc_dd);
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if (rc == 0)
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rtc_dd->use_uefi = true;
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}
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return 0;
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}
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static int pm8xxx_rtc_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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@ -469,6 +586,9 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
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if (rtc_dd == NULL)
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return -ENOMEM;
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rtc_dd->regs = match->data;
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rtc_dd->dev = &pdev->dev;
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rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!rtc_dd->regmap)
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return -ENXIO;
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@ -479,20 +599,8 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
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rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
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"allow-set-time");
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rtc_dd->nvmem_cell = devm_nvmem_cell_get(&pdev->dev, "offset");
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if (IS_ERR(rtc_dd->nvmem_cell)) {
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rc = PTR_ERR(rtc_dd->nvmem_cell);
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if (rc != -ENOENT)
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return rc;
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rtc_dd->nvmem_cell = NULL;
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}
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rtc_dd->regs = match->data;
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rtc_dd->dev = &pdev->dev;
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if (!rtc_dd->allow_set_time) {
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rc = pm8xxx_rtc_read_offset(rtc_dd);
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rc = pm8xxx_rtc_probe_offset(rtc_dd);
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if (rc)
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return rc;
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}
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@ -170,6 +170,7 @@ struct rtc_device {
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/* useful timestamps */
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#define RTC_TIMESTAMP_BEGIN_0000 -62167219200ULL /* 0000-01-01 00:00:00 */
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#define RTC_TIMESTAMP_BEGIN_1900 -2208988800LL /* 1900-01-01 00:00:00 */
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#define RTC_TIMESTAMP_EPOCH_GPS 315964800LL /* 1980-01-06 00:00:00 */
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#define RTC_TIMESTAMP_BEGIN_2000 946684800LL /* 2000-01-01 00:00:00 */
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#define RTC_TIMESTAMP_END_2063 2966371199LL /* 2063-12-31 23:59:59 */
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#define RTC_TIMESTAMP_END_2079 3471292799LL /* 2079-12-31 23:59:59 */
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