bus: mhi: host: pci_generic: Add support for SA8775P endpoint

Add MHI controller config for SA8775P endpoint. SA8775P supports IP_SW
usecase only. Hence use separate configuration to enable IP_SW channels.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20241205065422.2515086-2-quic_msarkar@quicinc.com
[mani: updated commit message and removed 'modem' reference in config]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Mrinmay Sarkar 2024-12-05 12:24:19 +05:30 committed by Manivannan Sadhasivam
parent c8006fbd0f
commit cba6bdfd79

View File

@ -297,6 +297,19 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
.sideband_wake = false,
};
static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = {
MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1),
MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2),
};
static struct mhi_event_config mhi_qcom_sa8775p_events[] = {
/* first ring is control+data ring */
MHI_EVENT_CONFIG_CTRL(0, 64),
/* Software channels dedicated event ring */
MHI_EVENT_CONFIG_SW_DATA(1, 64),
MHI_EVENT_CONFIG_SW_DATA(2, 64),
};
static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
@ -327,6 +340,15 @@ static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101)
};
static const struct mhi_controller_config mhi_qcom_sa8775p_config = {
.max_channels = 128,
.timeout_ms = 8000,
.num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels),
.ch_cfg = mhi_qcom_sa8775p_channels,
.num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events),
.event_cfg = mhi_qcom_sa8775p_events,
};
static const struct mhi_controller_config modem_qcom_v2_mhiv_config = {
.max_channels = 128,
.timeout_ms = 8000,
@ -346,6 +368,16 @@ static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
.event_cfg = modem_qcom_v1_mhi_events,
};
static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = {
.name = "qcom-sa8775p",
.edl_trigger = false,
.config = &mhi_qcom_sa8775p_config,
.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
.dma_data_width = 32,
.mru_default = 32768,
.sideband_wake = false,
};
static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = {
.name = "qcom-sdx75m",
.fw = "qcom/sdx75m/xbl.elf",
@ -772,6 +804,8 @@ static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = {
/* Keep the list sorted based on the PID. New VID should be added as the last entry */
static const struct pci_device_id mhi_pci_id_table[] = {
{PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116),
.driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info },
{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
.driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c),