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Merge branch 'pci/misc'
- Remove unused tools 'pci' build target left over after moving tests to tools/testing/selftests/pci_endpoint (Jianfeng Liu) - Fix typos and whitespace errors (Bjorn Helgaas) * pci/misc: PCI: Fix typos tools/Makefile: Remove pci target # Conflicts: # drivers/pci/endpoint/functions/pci-epf-test.c
This commit is contained in:
Bjorn Helgaas
commit
dea140198b
@ -301,12 +301,12 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
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val |= interrupts;
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cdns_pcie_ep_fn_writew(pcie, fn, reg, val);
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/* Set MSIX BAR and offset */
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/* Set MSI-X BAR and offset */
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reg = cap + PCI_MSIX_TABLE;
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val = offset | bir;
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cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
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/* Set PBA BAR and offset. BAR must match MSIX BAR */
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/* Set PBA BAR and offset. BAR must match MSI-X BAR */
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reg = cap + PCI_MSIX_PBA;
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val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
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cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
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@ -572,8 +572,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
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/*
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* Next function field in ARI_CAP_AND_CTR register for last function
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* should be 0.
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* Clearing Next Function Number field for the last function used.
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* should be 0. Clear Next Function Number field for the last
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* function used.
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*/
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last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG);
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reg = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn);
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@ -48,7 +48,7 @@
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#define PARF_DBI_BASE_ADDR_HI 0x354
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#define PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
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#define PARF_NO_SNOOP_OVERIDE 0x3d4
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#define PARF_NO_SNOOP_OVERRIDE 0x3d4
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#define PARF_ATU_BASE_ADDR 0x634
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#define PARF_ATU_BASE_ADDR_HI 0x638
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#define PARF_SRIS_MODE 0x644
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@ -89,9 +89,9 @@
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#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
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#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
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/* PARF_NO_SNOOP_OVERIDE register fields */
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#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
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#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
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/* PARF_NO_SNOOP_OVERRIDE register fields */
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#define WR_NO_SNOOP_OVERRIDE_EN BIT(1)
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#define RD_NO_SNOOP_OVERRIDE_EN BIT(3)
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/* PARF_DEVICE_TYPE register fields */
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#define PARF_DEVICE_TYPE_EP 0x0
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@ -529,8 +529,8 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
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writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
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if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop)
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writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
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pcie_ep->parf + PARF_NO_SNOOP_OVERIDE);
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writel_relaxed(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
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pcie_ep->parf + PARF_NO_SNOOP_OVERRIDE);
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return 0;
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@ -61,7 +61,7 @@
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#define PARF_DBI_BASE_ADDR_V2_HI 0x354
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#define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358
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#define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c
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#define PARF_NO_SNOOP_OVERIDE 0x3d4
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#define PARF_NO_SNOOP_OVERRIDE 0x3d4
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#define PARF_ATU_BASE_ADDR 0x634
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#define PARF_ATU_BASE_ADDR_HI 0x638
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#define PARF_DEVICE_TYPE 0x1000
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@ -135,9 +135,9 @@
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#define PARF_INT_ALL_LINK_UP BIT(13)
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#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
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/* PARF_NO_SNOOP_OVERIDE register fields */
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#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
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#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
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/* PARF_NO_SNOOP_OVERRIDE register fields */
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#define WR_NO_SNOOP_OVERRIDE_EN BIT(1)
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#define RD_NO_SNOOP_OVERRIDE_EN BIT(3)
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/* PARF_DEVICE_TYPE register fields */
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#define DEVICE_TYPE_RC 0x4
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@ -1007,8 +1007,8 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
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const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
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if (pcie_cfg->override_no_snoop)
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writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
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pcie->parf + PARF_NO_SNOOP_OVERIDE);
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writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
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pcie->parf + PARF_NO_SNOOP_OVERRIDE);
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qcom_pcie_clear_aspm_l0s(pcie->pci);
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qcom_pcie_clear_hpc(pcie->pci);
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@ -1422,7 +1422,7 @@ static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
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}
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/*
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* devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
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* devm_of_pci_get_host_bridge_resources() only sets up translatable resources,
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* so we need extra resource setup parsing our special DT properties encoding
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* the MEM and IO apertures.
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*/
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@ -204,7 +204,7 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
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v = readl(addr);
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if (v & 0xff00)
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pr_err("Bad MSIX cap header: %08x\n", v);
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pr_err("Bad MSI-X cap header: %08x\n", v);
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v |= 0xbc00; /* next capability is EA at 0xbc */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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@ -154,7 +154,7 @@ static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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* X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain
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* the expected behaviour of .set_affinity for each MSI interrupt, the 16
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* MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs
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* for each core). The MSI vector is moved fom 1 MSI GIC IRQ to another
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* for each core). The MSI vector is moved from 1 MSI GIC IRQ to another
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* MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a
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* consequence, the total MSI vectors that X-Gene v1 supports will be
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* reduced to 256 (2048/8) vectors.
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@ -205,7 +205,7 @@ static bool aglx_altera_pcie_link_up(struct altera_pcie *pcie)
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* Altera PCIe port uses BAR0 of RC's configuration space as the translation
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* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
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* using these registers, so it can be reached by DMA from EP devices.
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* This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
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* This BAR0 will also access to MSI vector when receiving MSI/MSI-X interrupt
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* from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
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* should be hidden during enumeration to avoid the sizing and resource
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* allocation by PCIe core.
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@ -40,7 +40,7 @@
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/* Broadcom STB PCIe Register Offsets */
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#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
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#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
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#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
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#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
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#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
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#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
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@ -1222,7 +1222,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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/* PCIe->SCB endian mode for inbound window */
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tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
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u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN,
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PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
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writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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@ -178,8 +178,8 @@ static int rcar_pcie_config_access(struct rcar_pcie_host *host,
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* space, it's generally only accessible when in endpoint mode.
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* When in root complex mode, the controller is unable to target
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* itself with either type 0 or type 1 accesses, and indeed, any
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* controller initiated target transfer to its own config space
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* result in a completer abort.
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* controller-initiated target transfer to its own config space
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* results in a completer abort.
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*
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* Each channel effectively only supports a single device, but as
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* the same channel <-> device access works for any PCI_SLOT()
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@ -775,7 +775,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
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if (err)
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return err;
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/* Two irqs are for MSI, but they are also used for non-MSI irqs */
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/* Two IRQs are for MSI, but they are also used for non-MSI IRQs */
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err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
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IRQF_SHARED | IRQF_NO_THREAD,
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rcar_msi_bottom_chip.name, host);
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@ -792,7 +792,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
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goto err;
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}
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/* disable all MSIs */
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/* Disable all MSIs */
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rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
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/*
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@ -892,6 +892,7 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
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dev_err(pcie->dev, "Failed to map inbound regions!\n");
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return -EINVAL;
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}
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/*
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* If the size of the range is larger than the alignment of
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* the start address, we have to use multiple entries to
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@ -903,6 +904,7 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
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size = min(size, alignment);
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}
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/* Hardware supports max 4GiB inbound region */
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size = min(size, 1ULL << 32);
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@ -26,7 +26,7 @@ config PCI_ENDPOINT_CONFIGFS
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help
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This will enable the configfs entry that can be used to
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configure the endpoint function and used to bind the
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function with a endpoint controller.
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function with an endpoint controller.
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source "drivers/pci/endpoint/functions/Kconfig"
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@ -654,7 +654,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
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case IRQ_TYPE_MSIX:
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count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
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if (irq_number > count || count <= 0) {
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dev_err(dev, "Invalid MSIX IRQ number %d / %d\n",
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dev_err(dev, "Invalid MSI-X IRQ number %d / %d\n",
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irq_number, count);
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return;
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}
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@ -97,7 +97,7 @@ config HOTPLUG_PCI_CPCI_ZT5550
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tristate "Ziatech ZT5550 CompactPCI Hotplug driver"
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depends on HOTPLUG_PCI_CPCI && X86
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help
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Say Y here if you have an Performance Technologies (formerly Intel,
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Say Y here if you have a Performance Technologies (formerly Intel,
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formerly just Ziatech) Ziatech ZT5550 CompactPCI system card.
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To compile this driver as a module, choose M here: the
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@ -431,7 +431,7 @@ void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
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* removed immediately after the check so the caller may need to take
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* this into account.
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*
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* It the hotplug controller itself is not available anymore returns
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* If the hotplug controller itself is not available anymore returns
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* %-ENODEV.
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*/
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int pciehp_card_present(struct controller *ctrl)
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@ -162,7 +162,7 @@ struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
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EXPORT_SYMBOL_GPL(pci_msix_alloc_irq_at);
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/**
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* pci_msix_free_irq - Free an interrupt on a PCI/MSIX interrupt domain
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* pci_msix_free_irq - Free an interrupt on a PCI/MSI-X interrupt domain
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*
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* @dev: The PCI device to operate on
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* @map: A struct msi_map describing the interrupt to free
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@ -455,9 +455,9 @@ failed:
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* @out_irq: structure of_phandle_args filled by this function
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*
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* This function resolves the PCI interrupt for a given PCI device. If a
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* device-node exists for a given pci_dev, it will use normal OF tree
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* device node exists for a given pci_dev, it will use normal OF tree
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* walking. If not, it will implement standard swizzling and walk up the
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* PCI tree until an device-node is found, at which point it will finish
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* PCI tree until a device node is found, at which point it will finish
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* resolving using the OF tree walking.
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*/
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static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
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@ -517,13 +517,16 @@ static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *
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}
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/*
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* Ok, we have found a parent with a device-node, hand over to
|
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* Ok, we have found a parent with a device node, hand over to
|
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* the OF parsing code.
|
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*
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* We build a unit address from the linux device to be used for
|
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* resolution. Note that we use the linux bus number which may
|
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* not match your firmware bus numbering.
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*
|
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* Fortunately, in most cases, interrupt-map-mask doesn't
|
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* include the bus number as part of the matching.
|
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*
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* You should still be careful about that though if you intend
|
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* to rely on this function (you ship a firmware that doesn't
|
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* create device nodes for all PCI devices).
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@ -4785,7 +4785,7 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
|
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/*
|
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* PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
|
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* after which we should expect an link active if the reset was
|
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* after which we should expect the link to be active if the reset was
|
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* successful. If so, software must wait a minimum 100ms before sending
|
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* configuration requests to devices downstream this port.
|
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*
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@ -2,7 +2,7 @@
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/*
|
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* Implement the AER root port service driver. The driver registers an IRQ
|
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* handler. When a root port triggers an AER interrupt, the IRQ handler
|
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* collects root port status and schedules work.
|
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* collects Root Port status and schedules work.
|
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*
|
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* Copyright (C) 2006 Intel Corp.
|
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* Tom Long Nguyen (tom.l.nguyen@intel.com)
|
||||
@ -60,9 +60,9 @@ struct aer_stats {
|
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/*
|
||||
* Fields for all AER capable devices. They indicate the errors
|
||||
* "as seen by this device". Note that this may mean that if an
|
||||
* end point is causing problems, the AER counters may increment
|
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* at its link partner (e.g. root port) because the errors will be
|
||||
* "seen" by the link partner and not the problematic end point
|
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* Endpoint is causing problems, the AER counters may increment
|
||||
* at its link partner (e.g. Root Port) because the errors will be
|
||||
* "seen" by the link partner and not the problematic Endpoint
|
||||
* itself (which may report all counters as 0 as it never saw any
|
||||
* problems).
|
||||
*/
|
||||
@ -80,10 +80,10 @@ struct aer_stats {
|
||||
u64 dev_total_nonfatal_errs;
|
||||
|
||||
/*
|
||||
* Fields for Root ports & root complex event collectors only, these
|
||||
* Fields for Root Ports & Root Complex Event Collectors only; these
|
||||
* indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
|
||||
* messages received by the root port / event collector, INCLUDING the
|
||||
* ones that are generated internally (by the rootport itself)
|
||||
* messages received by the Root Port / Event Collector, INCLUDING the
|
||||
* ones that are generated internally (by the Root Port itself)
|
||||
*/
|
||||
u64 rootport_total_cor_errs;
|
||||
u64 rootport_total_fatal_errs;
|
||||
@ -142,7 +142,7 @@ static const char * const ecrc_policy_str[] = {
|
||||
* enable_ecrc_checking - enable PCIe ECRC checking for a device
|
||||
* @dev: the PCI device
|
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*
|
||||
* Returns 0 on success, or negative on failure.
|
||||
* Return: 0 on success, or negative on failure.
|
||||
*/
|
||||
static int enable_ecrc_checking(struct pci_dev *dev)
|
||||
{
|
||||
@ -163,10 +163,10 @@ static int enable_ecrc_checking(struct pci_dev *dev)
|
||||
}
|
||||
|
||||
/**
|
||||
* disable_ecrc_checking - disables PCIe ECRC checking for a device
|
||||
* disable_ecrc_checking - disable PCIe ECRC checking for a device
|
||||
* @dev: the PCI device
|
||||
*
|
||||
* Returns 0 on success, or negative on failure.
|
||||
* Return: 0 on success, or negative on failure.
|
||||
*/
|
||||
static int disable_ecrc_checking(struct pci_dev *dev)
|
||||
{
|
||||
@ -287,10 +287,10 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev)
|
||||
* pci_aer_raw_clear_status - Clear AER error registers.
|
||||
* @dev: the PCI device
|
||||
*
|
||||
* Clearing AER error status registers unconditionally, regardless of
|
||||
* Clear AER error status registers unconditionally, regardless of
|
||||
* whether they're owned by firmware or the OS.
|
||||
*
|
||||
* Returns 0 on success, or negative on failure.
|
||||
* Return: 0 on success, or negative on failure.
|
||||
*/
|
||||
int pci_aer_raw_clear_status(struct pci_dev *dev)
|
||||
{
|
||||
@ -382,8 +382,8 @@ void pci_aer_init(struct pci_dev *dev)
|
||||
/*
|
||||
* We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
|
||||
* PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
|
||||
* Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
|
||||
* 7.8.4).
|
||||
* Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r6.0, sec
|
||||
* 7.8.4.9).
|
||||
*/
|
||||
n = pcie_cap_has_rtctl(dev) ? 5 : 4;
|
||||
pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
|
||||
@ -829,8 +829,8 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
|
||||
u16 reg16;
|
||||
|
||||
/*
|
||||
* When bus id is equal to 0, it might be a bad id
|
||||
* reported by root port.
|
||||
* When bus ID is equal to 0, it might be a bad ID
|
||||
* reported by Root Port.
|
||||
*/
|
||||
if ((PCI_BUS_NUM(e_info->id) != 0) &&
|
||||
!(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
|
||||
@ -838,15 +838,15 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
|
||||
if (e_info->id == pci_dev_id(dev))
|
||||
return true;
|
||||
|
||||
/* Continue id comparing if there is no multiple error */
|
||||
/* Continue ID comparing if there is no multiple error */
|
||||
if (!e_info->multi_error_valid)
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* When either
|
||||
* 1) bus id is equal to 0. Some ports might lose the bus
|
||||
* id of error source id;
|
||||
* 1) bus ID is equal to 0. Some ports might lose the bus
|
||||
* ID of error source id;
|
||||
* 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
|
||||
* 3) There are multiple errors and prior ID comparing fails;
|
||||
* We check AER status registers to find possible reporter.
|
||||
@ -898,9 +898,9 @@ static int find_device_iter(struct pci_dev *dev, void *data)
|
||||
/**
|
||||
* find_source_device - search through device hierarchy for source device
|
||||
* @parent: pointer to Root Port pci_dev data structure
|
||||
* @e_info: including detailed error information such like id
|
||||
* @e_info: including detailed error information such as ID
|
||||
*
|
||||
* Return true if found.
|
||||
* Return: true if found.
|
||||
*
|
||||
* Invoked by DPC when error is detected at the Root Port.
|
||||
* Caller of this function must set id, severity, and multi_error_valid of
|
||||
@ -942,9 +942,9 @@ static bool find_source_device(struct pci_dev *parent,
|
||||
|
||||
/**
|
||||
* pci_aer_unmask_internal_errors - unmask internal errors
|
||||
* @dev: pointer to the pcie_dev data structure
|
||||
* @dev: pointer to the pci_dev data structure
|
||||
*
|
||||
* Unmasks internal errors in the Uncorrectable and Correctable Error
|
||||
* Unmask internal errors in the Uncorrectable and Correctable Error
|
||||
* Mask registers.
|
||||
*
|
||||
* Note: AER must be enabled and supported by the device which must be
|
||||
@ -1007,7 +1007,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
|
||||
if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
|
||||
return 0;
|
||||
|
||||
/* protect dev->driver */
|
||||
/* Protect dev->driver */
|
||||
device_lock(&dev->dev);
|
||||
|
||||
err_handler = dev->driver ? dev->driver->err_handler : NULL;
|
||||
@ -1199,10 +1199,10 @@ EXPORT_SYMBOL_GPL(aer_recover_queue);
|
||||
|
||||
/**
|
||||
* aer_get_device_error_info - read error status from dev and store it to info
|
||||
* @dev: pointer to the device expected to have a error record
|
||||
* @dev: pointer to the device expected to have an error record
|
||||
* @info: pointer to structure to store the error record
|
||||
*
|
||||
* Return 1 on success, 0 on error.
|
||||
* Return: 1 on success, 0 on error.
|
||||
*
|
||||
* Note that @info is reused among all error devices. Clear fields properly.
|
||||
*/
|
||||
@ -1261,7 +1261,7 @@ static inline void aer_process_err_devices(struct aer_err_info *e_info)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Report all before handle them, not to lost records by reset etc. */
|
||||
/* Report all before handling them, to not lose records by reset etc. */
|
||||
for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
|
||||
if (aer_get_device_error_info(e_info->dev[i], e_info))
|
||||
aer_print_error(e_info->dev[i], e_info);
|
||||
@ -1273,8 +1273,8 @@ static inline void aer_process_err_devices(struct aer_err_info *e_info)
|
||||
}
|
||||
|
||||
/**
|
||||
* aer_isr_one_error - consume an error detected by root port
|
||||
* @rpc: pointer to the root port which holds an error
|
||||
* aer_isr_one_error - consume an error detected by Root Port
|
||||
* @rpc: pointer to the Root Port which holds an error
|
||||
* @e_src: pointer to an error source
|
||||
*/
|
||||
static void aer_isr_one_error(struct aer_rpc *rpc,
|
||||
@ -1324,11 +1324,11 @@ static void aer_isr_one_error(struct aer_rpc *rpc,
|
||||
}
|
||||
|
||||
/**
|
||||
* aer_isr - consume errors detected by root port
|
||||
* aer_isr - consume errors detected by Root Port
|
||||
* @irq: IRQ assigned to Root Port
|
||||
* @context: pointer to Root Port data structure
|
||||
*
|
||||
* Invoked, as DPC, when root port records new detected error
|
||||
* Invoked, as DPC, when Root Port records new detected error
|
||||
*/
|
||||
static irqreturn_t aer_isr(int irq, void *context)
|
||||
{
|
||||
@ -1388,7 +1388,7 @@ static void aer_disable_irq(struct pci_dev *pdev)
|
||||
int aer = pdev->aer_cap;
|
||||
u32 reg32;
|
||||
|
||||
/* Disable Root's interrupt in response to error messages */
|
||||
/* Disable Root Port's interrupt in response to error messages */
|
||||
pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
|
||||
reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
|
||||
pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
|
||||
@ -1588,9 +1588,9 @@ static struct pcie_port_service_driver aerdriver = {
|
||||
};
|
||||
|
||||
/**
|
||||
* pcie_aer_init - register AER root service driver
|
||||
* pcie_aer_init - register AER service driver
|
||||
*
|
||||
* Invoked when AER root service driver is loaded.
|
||||
* Invoked when AER service driver is loaded.
|
||||
*/
|
||||
int __init pcie_aer_init(void)
|
||||
{
|
||||
|
||||
@ -1990,7 +1990,7 @@ static void remove_dev_resources(struct pci_dev *dev, struct resource *io,
|
||||
* Make sure prefetchable memory is reduced from
|
||||
* the correct resource. Specifically we put 32-bit
|
||||
* prefetchable memory in non-prefetchable window
|
||||
* if there is an 64-bit prefetchable window.
|
||||
* if there is a 64-bit prefetchable window.
|
||||
*
|
||||
* See comments in __pci_bus_size_bridges() for
|
||||
* more information.
|
||||
|
||||
@ -38,7 +38,7 @@ enum pci_barno {
|
||||
* @baseclass_code: broadly classifies the type of function the device performs
|
||||
* @cache_line_size: specifies the system cacheline size in units of DWORDs
|
||||
* @subsys_vendor_id: vendor of the add-in card or subsystem
|
||||
* @subsys_id: id specific to vendor
|
||||
* @subsys_id: ID specific to vendor
|
||||
* @interrupt_pin: interrupt pin the device (or device function) uses
|
||||
*/
|
||||
struct pci_epf_header {
|
||||
@ -59,7 +59,7 @@ struct pci_epf_header {
|
||||
* @bind: ops to perform when a EPC device has been bound to EPF device
|
||||
* @unbind: ops to perform when a binding has been lost between a EPC device
|
||||
* and EPF device
|
||||
* @add_cfs: ops to initialize function specific configfs attributes
|
||||
* @add_cfs: ops to initialize function-specific configfs attributes
|
||||
*/
|
||||
struct pci_epf_ops {
|
||||
int (*bind)(struct pci_epf *epf);
|
||||
@ -138,7 +138,7 @@ struct pci_epf_bar {
|
||||
* @epc: the EPC device to which this EPF device is bound
|
||||
* @epf_pf: the physical EPF device to which this virtual EPF device is bound
|
||||
* @driver: the EPF driver to which this EPF device is bound
|
||||
* @id: Pointer to the EPF device ID
|
||||
* @id: pointer to the EPF device ID
|
||||
* @list: to add pci_epf as a list of PCI endpoint functions to pci_epc
|
||||
* @lock: mutex to protect pci_epf_ops
|
||||
* @sec_epc: the secondary EPC device to which this EPF device is bound
|
||||
@ -151,7 +151,7 @@ struct pci_epf_bar {
|
||||
* @is_vf: true - virtual function, false - physical function
|
||||
* @vfunction_num_map: bitmap to manage virtual function number
|
||||
* @pci_vepf: list of virtual endpoint functions associated with this function
|
||||
* @event_ops: Callbacks for capturing the EPC events
|
||||
* @event_ops: callbacks for capturing the EPC events
|
||||
*/
|
||||
struct pci_epf {
|
||||
struct device dev;
|
||||
@ -185,11 +185,12 @@ struct pci_epf {
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pci_epf_msix_tbl - represents the MSIX table entry structure
|
||||
* @msg_addr: Writes to this address will trigger MSIX interrupt in host
|
||||
* @msg_data: Data that should be written to @msg_addr to trigger MSIX interrupt
|
||||
* struct pci_epf_msix_tbl - represents the MSI-X table entry structure
|
||||
* @msg_addr: Writes to this address will trigger MSI-X interrupt in host
|
||||
* @msg_data: Data that should be written to @msg_addr to trigger MSI-X
|
||||
* interrupt
|
||||
* @vector_ctrl: Identifies if the function is prohibited from sending a message
|
||||
* using this MSIX table entry
|
||||
* using this MSI-X table entry
|
||||
*/
|
||||
struct pci_epf_msix_tbl {
|
||||
u64 msg_addr;
|
||||
|
||||
@ -25,7 +25,6 @@ help:
|
||||
@echo ' leds - LEDs tools'
|
||||
@echo ' nolibc - nolibc headers testing and installation'
|
||||
@echo ' objtool - an ELF object analysis tool'
|
||||
@echo ' pci - PCI tools'
|
||||
@echo ' perf - Linux performance measurement and analysis tool'
|
||||
@echo ' selftests - various kernel selftests'
|
||||
@echo ' sched_ext - sched_ext example schedulers'
|
||||
@ -69,7 +68,7 @@ acpi: FORCE
|
||||
cpupower: FORCE
|
||||
$(call descend,power/$@)
|
||||
|
||||
counter firewire hv guest bootconfig spi usb virtio mm bpf iio gpio objtool leds wmi pci firmware debugging tracing: FORCE
|
||||
counter firewire hv guest bootconfig spi usb virtio mm bpf iio gpio objtool leds wmi firmware debugging tracing: FORCE
|
||||
$(call descend,$@)
|
||||
|
||||
bpf/%: FORCE
|
||||
@ -123,7 +122,7 @@ all: acpi counter cpupower gpio hv firewire \
|
||||
perf selftests bootconfig spi turbostat usb \
|
||||
virtio mm bpf x86_energy_perf_policy \
|
||||
tmon freefall iio objtool kvm_stat wmi \
|
||||
pci debugging tracing thermal thermometer thermal-engine
|
||||
debugging tracing thermal thermometer thermal-engine
|
||||
|
||||
acpi_install:
|
||||
$(call descend,power/$(@:_install=),install)
|
||||
@ -131,7 +130,7 @@ acpi_install:
|
||||
cpupower_install:
|
||||
$(call descend,power/$(@:_install=),install)
|
||||
|
||||
counter_install firewire_install gpio_install hv_install iio_install perf_install bootconfig_install spi_install usb_install virtio_install mm_install bpf_install objtool_install wmi_install pci_install debugging_install tracing_install:
|
||||
counter_install firewire_install gpio_install hv_install iio_install perf_install bootconfig_install spi_install usb_install virtio_install mm_install bpf_install objtool_install wmi_install debugging_install tracing_install:
|
||||
$(call descend,$(@:_install=),install)
|
||||
|
||||
selftests_install:
|
||||
@ -163,7 +162,7 @@ install: acpi_install counter_install cpupower_install gpio_install \
|
||||
perf_install selftests_install turbostat_install usb_install \
|
||||
virtio_install mm_install bpf_install x86_energy_perf_policy_install \
|
||||
tmon_install freefall_install objtool_install kvm_stat_install \
|
||||
wmi_install pci_install debugging_install intel-speed-select_install \
|
||||
wmi_install debugging_install intel-speed-select_install \
|
||||
tracing_install thermometer_install thermal-engine_install
|
||||
|
||||
acpi_clean:
|
||||
@ -172,7 +171,7 @@ acpi_clean:
|
||||
cpupower_clean:
|
||||
$(call descend,power/cpupower,clean)
|
||||
|
||||
counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean pci_clean firmware_clean debugging_clean tracing_clean:
|
||||
counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean firmware_clean debugging_clean tracing_clean:
|
||||
$(call descend,$(@:_clean=),clean)
|
||||
|
||||
libapi_clean:
|
||||
@ -219,7 +218,7 @@ clean: acpi_clean counter_clean cpupower_clean hv_clean firewire_clean \
|
||||
perf_clean selftests_clean turbostat_clean bootconfig_clean spi_clean usb_clean virtio_clean \
|
||||
mm_clean bpf_clean iio_clean x86_energy_perf_policy_clean tmon_clean \
|
||||
freefall_clean build_clean libbpf_clean libsubcmd_clean \
|
||||
gpio_clean objtool_clean leds_clean wmi_clean pci_clean firmware_clean debugging_clean \
|
||||
gpio_clean objtool_clean leds_clean wmi_clean firmware_clean debugging_clean \
|
||||
intel-speed-select_clean tracing_clean thermal_clean thermometer_clean thermal-engine_clean \
|
||||
sched_ext_clean
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user