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On ARMv7 / v7m machines read CTR and CLIDR registers to provide information regarding the cache topology. Earlier machines should describe full cache topology in the device tree. Note, this follows the ARM64 cacheinfo support and provides only minimal support required to bootstrap cache info. All useful properties should be decribed in Device Tree. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
36 lines
896 B
C
36 lines
896 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/include/asm/cache.h
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*/
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#ifndef __ASMARM_CACHE_H
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#define __ASMARM_CACHE_H
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#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/*
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* Memory returned by kmalloc() may be used for DMA, so we must make
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* sure that all such allocations are cache aligned. Otherwise,
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* unrelated code may cause parts of the buffer to be read into the
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* cache before the transfer is done, causing old data to be seen by
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* the CPU.
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*/
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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/*
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* With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
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*/
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#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
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#define ARCH_SLAB_MINALIGN 8
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#endif
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#define __read_mostly __section(".data..read_mostly")
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
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int cache_line_size(void);
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#endif
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#endif
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#endif
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