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04816c1507
We need to switch SFB (Store Fill Buffer) and TSO (Total Store Order) state at runtime to debug memory management and KVM virtualization, so add two debugfs entries "sfb_state" and "tso_state" under the directory /sys/kernel/debug/loongarch. Query SFB: cat /sys/kernel/debug/loongarch/sfb_state Enable SFB: echo 1 > /sys/kernel/debug/loongarch/sfb_state Disable SFB: echo 0 > /sys/kernel/debug/loongarch/sfb_state Query TSO: cat /sys/kernel/debug/loongarch/tso_state Switch TSO: echo [TSO] > /sys/kernel/debug/loongarch/tso_state Available [TSO] states: 0 (No Load No Store) 1 (All Load No Store) 3 (Same Load No Store) 4 (No Load All Store) 5 (All Load All Store) 7 (Same Load All Store) Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
494 lines
7.8 KiB
C
494 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Handle unaligned accesses by emulation.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2014 Imagination Technologies Ltd.
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*/
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/debugfs.h>
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#include <linux/perf_event.h>
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#include <asm/asm.h>
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#include <asm/branch.h>
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#include <asm/fpu.h>
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#include <asm/inst.h>
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#include "access-helper.h"
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#ifdef CONFIG_DEBUG_FS
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static u32 unaligned_instructions_user;
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static u32 unaligned_instructions_kernel;
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#endif
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static inline unsigned long read_fpr(unsigned int idx)
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{
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#define READ_FPR(idx, __value) \
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__asm__ __volatile__("movfr2gr.d %0, $f"#idx"\n\t" : "=r"(__value));
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unsigned long __value;
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switch (idx) {
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case 0:
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READ_FPR(0, __value);
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break;
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case 1:
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READ_FPR(1, __value);
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break;
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case 2:
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READ_FPR(2, __value);
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break;
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case 3:
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READ_FPR(3, __value);
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break;
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case 4:
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READ_FPR(4, __value);
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break;
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case 5:
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READ_FPR(5, __value);
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break;
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case 6:
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READ_FPR(6, __value);
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break;
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case 7:
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READ_FPR(7, __value);
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break;
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case 8:
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READ_FPR(8, __value);
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break;
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case 9:
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READ_FPR(9, __value);
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break;
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case 10:
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READ_FPR(10, __value);
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break;
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case 11:
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READ_FPR(11, __value);
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break;
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case 12:
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READ_FPR(12, __value);
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break;
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case 13:
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READ_FPR(13, __value);
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break;
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case 14:
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READ_FPR(14, __value);
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break;
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case 15:
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READ_FPR(15, __value);
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break;
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case 16:
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READ_FPR(16, __value);
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break;
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case 17:
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READ_FPR(17, __value);
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break;
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case 18:
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READ_FPR(18, __value);
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break;
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case 19:
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READ_FPR(19, __value);
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break;
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case 20:
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READ_FPR(20, __value);
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break;
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case 21:
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READ_FPR(21, __value);
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break;
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case 22:
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READ_FPR(22, __value);
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break;
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case 23:
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READ_FPR(23, __value);
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break;
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case 24:
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READ_FPR(24, __value);
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break;
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case 25:
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READ_FPR(25, __value);
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break;
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case 26:
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READ_FPR(26, __value);
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break;
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case 27:
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READ_FPR(27, __value);
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break;
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case 28:
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READ_FPR(28, __value);
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break;
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case 29:
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READ_FPR(29, __value);
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break;
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case 30:
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READ_FPR(30, __value);
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break;
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case 31:
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READ_FPR(31, __value);
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break;
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default:
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panic("unexpected idx '%d'", idx);
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}
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#undef READ_FPR
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return __value;
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}
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static inline void write_fpr(unsigned int idx, unsigned long value)
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{
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#define WRITE_FPR(idx, value) \
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__asm__ __volatile__("movgr2fr.d $f"#idx", %0\n\t" :: "r"(value));
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switch (idx) {
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case 0:
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WRITE_FPR(0, value);
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break;
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case 1:
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WRITE_FPR(1, value);
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break;
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case 2:
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WRITE_FPR(2, value);
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break;
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case 3:
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WRITE_FPR(3, value);
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break;
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case 4:
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WRITE_FPR(4, value);
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break;
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case 5:
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WRITE_FPR(5, value);
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break;
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case 6:
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WRITE_FPR(6, value);
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break;
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case 7:
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WRITE_FPR(7, value);
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break;
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case 8:
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WRITE_FPR(8, value);
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break;
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case 9:
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WRITE_FPR(9, value);
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break;
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case 10:
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WRITE_FPR(10, value);
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break;
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case 11:
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WRITE_FPR(11, value);
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break;
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case 12:
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WRITE_FPR(12, value);
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break;
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case 13:
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WRITE_FPR(13, value);
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break;
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case 14:
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WRITE_FPR(14, value);
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break;
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case 15:
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WRITE_FPR(15, value);
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break;
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case 16:
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WRITE_FPR(16, value);
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break;
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case 17:
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WRITE_FPR(17, value);
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break;
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case 18:
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WRITE_FPR(18, value);
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break;
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case 19:
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WRITE_FPR(19, value);
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break;
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case 20:
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WRITE_FPR(20, value);
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break;
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case 21:
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WRITE_FPR(21, value);
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break;
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case 22:
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WRITE_FPR(22, value);
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break;
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case 23:
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WRITE_FPR(23, value);
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break;
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case 24:
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WRITE_FPR(24, value);
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break;
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case 25:
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WRITE_FPR(25, value);
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break;
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case 26:
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WRITE_FPR(26, value);
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break;
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case 27:
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WRITE_FPR(27, value);
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break;
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case 28:
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WRITE_FPR(28, value);
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break;
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case 29:
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WRITE_FPR(29, value);
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break;
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case 30:
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WRITE_FPR(30, value);
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break;
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case 31:
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WRITE_FPR(31, value);
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break;
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default:
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panic("unexpected idx '%d'", idx);
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}
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#undef WRITE_FPR
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}
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void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc)
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{
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bool fp = false;
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bool sign, write;
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bool user = user_mode(regs);
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unsigned int res, size = 0;
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unsigned long value = 0;
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union loongarch_instruction insn;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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__get_inst(&insn.word, pc, user);
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switch (insn.reg2i12_format.opcode) {
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case ldh_op:
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size = 2;
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sign = true;
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write = false;
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break;
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case ldhu_op:
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size = 2;
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sign = false;
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write = false;
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break;
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case sth_op:
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size = 2;
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sign = true;
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write = true;
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break;
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case ldw_op:
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size = 4;
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sign = true;
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write = false;
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break;
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case ldwu_op:
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size = 4;
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sign = false;
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write = false;
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break;
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case stw_op:
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size = 4;
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sign = true;
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write = true;
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break;
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case ldd_op:
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size = 8;
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sign = true;
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write = false;
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break;
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case std_op:
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size = 8;
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sign = true;
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write = true;
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break;
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case flds_op:
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size = 4;
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fp = true;
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sign = true;
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write = false;
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break;
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case fsts_op:
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size = 4;
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fp = true;
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sign = true;
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write = true;
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break;
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case fldd_op:
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size = 8;
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fp = true;
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sign = true;
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write = false;
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break;
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case fstd_op:
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size = 8;
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fp = true;
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sign = true;
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write = true;
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break;
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}
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switch (insn.reg2i14_format.opcode) {
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case ldptrw_op:
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size = 4;
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sign = true;
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write = false;
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break;
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case stptrw_op:
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size = 4;
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sign = true;
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write = true;
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break;
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case ldptrd_op:
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size = 8;
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sign = true;
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write = false;
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break;
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case stptrd_op:
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size = 8;
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sign = true;
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write = true;
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break;
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}
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switch (insn.reg3_format.opcode) {
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case ldxh_op:
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size = 2;
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sign = true;
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write = false;
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break;
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case ldxhu_op:
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size = 2;
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sign = false;
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write = false;
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break;
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case stxh_op:
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size = 2;
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sign = true;
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write = true;
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break;
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case ldxw_op:
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size = 4;
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sign = true;
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write = false;
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break;
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case ldxwu_op:
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size = 4;
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sign = false;
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write = false;
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break;
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case stxw_op:
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size = 4;
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sign = true;
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write = true;
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break;
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case ldxd_op:
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size = 8;
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sign = true;
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write = false;
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break;
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case stxd_op:
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size = 8;
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sign = true;
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write = true;
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break;
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case fldxs_op:
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size = 4;
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fp = true;
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sign = true;
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write = false;
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break;
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case fstxs_op:
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size = 4;
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fp = true;
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sign = true;
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write = true;
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break;
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case fldxd_op:
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size = 8;
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fp = true;
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sign = true;
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write = false;
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break;
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case fstxd_op:
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size = 8;
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fp = true;
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sign = true;
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write = true;
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break;
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}
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if (!size)
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goto sigbus;
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if (user && !access_ok(addr, size))
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goto sigbus;
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if (!write) {
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res = unaligned_read(addr, &value, size, sign);
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if (res)
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goto fault;
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/* Rd is the same field in any formats */
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if (!fp)
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regs->regs[insn.reg3_format.rd] = value;
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else {
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if (is_fpu_owner())
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write_fpr(insn.reg3_format.rd, value);
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else
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set_fpr64(¤t->thread.fpu.fpr[insn.reg3_format.rd], 0, value);
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}
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} else {
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/* Rd is the same field in any formats */
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if (!fp)
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value = regs->regs[insn.reg3_format.rd];
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else {
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if (is_fpu_owner())
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value = read_fpr(insn.reg3_format.rd);
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else
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value = get_fpr64(¤t->thread.fpu.fpr[insn.reg3_format.rd], 0);
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}
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res = unaligned_write(addr, value, size);
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if (res)
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goto fault;
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}
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#ifdef CONFIG_DEBUG_FS
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if (user)
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unaligned_instructions_user++;
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else
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unaligned_instructions_kernel++;
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#endif
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compute_return_era(regs);
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return;
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fault:
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/* Did we have an exception handler installed? */
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if (fixup_exception(regs))
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return;
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die_if_kernel("Unhandled kernel unaligned access", regs);
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force_sig(SIGSEGV);
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return;
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sigbus:
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die_if_kernel("Unhandled kernel unaligned access", regs);
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force_sig(SIGBUS);
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return;
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}
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#ifdef CONFIG_DEBUG_FS
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static int __init debugfs_unaligned(void)
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{
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debugfs_create_u32("unaligned_instructions_user",
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S_IRUGO, arch_debugfs_dir, &unaligned_instructions_user);
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debugfs_create_u32("unaligned_instructions_kernel",
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S_IRUGO, arch_debugfs_dir, &unaligned_instructions_kernel);
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return 0;
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}
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arch_initcall(debugfs_unaligned);
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#endif
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