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two locking commits in the locking tree, part of the locking-core-2025-03-22 pull request. ] x86 CPU features support: - Generate the <asm/cpufeaturemasks.h> header based on build config (H. Peter Anvin, Xin Li) - x86 CPUID parsing updates and fixes (Ahmed S. Darwish) - Introduce the 'setcpuid=' boot parameter (Brendan Jackman) - Enable modifying CPU bug flags with '{clear,set}puid=' (Brendan Jackman) - Utilize CPU-type for CPU matching (Pawan Gupta) - Warn about unmet CPU feature dependencies (Sohil Mehta) - Prepare for new Intel Family numbers (Sohil Mehta) Percpu code: - Standardize & reorganize the x86 percpu layout and related cleanups (Brian Gerst) - Convert the stackprotector canary to a regular percpu variable (Brian Gerst) - Add a percpu subsection for cache hot data (Brian Gerst) - Unify __pcpu_op{1,2}_N() macros to __pcpu_op_N() (Uros Bizjak) - Construct __percpu_seg_override from __percpu_seg (Uros Bizjak) MM: - Add support for broadcast TLB invalidation using AMD's INVLPGB instruction (Rik van Riel) - Rework ROX cache to avoid writable copy (Mike Rapoport) - PAT: restore large ROX pages after fragmentation (Kirill A. Shutemov, Mike Rapoport) - Make memremap(MEMREMAP_WB) map memory as encrypted by default (Kirill A. Shutemov) - Robustify page table initialization (Kirill A. Shutemov) - Fix flush_tlb_range() when used for zapping normal PMDs (Jann Horn) - Clear _PAGE_DIRTY for kernel mappings when we clear _PAGE_RW (Matthew Wilcox) KASLR: - x86/kaslr: Reduce KASLR entropy on most x86 systems, to support PCI BAR space beyond the 10TiB region (CONFIG_PCI_P2PDMA=y) (Balbir Singh) CPU bugs: - Implement FineIBT-BHI mitigation (Peter Zijlstra) - speculation: Simplify and make CALL_NOSPEC consistent (Pawan Gupta) - speculation: Add a conditional CS prefix to CALL_NOSPEC (Pawan Gupta) - RFDS: Exclude P-only parts from the RFDS affected list (Pawan Gupta) System calls: - Break up entry/common.c (Brian Gerst) - Move sysctls into arch/x86 (Joel Granados) Intel LAM support updates: (Maciej Wieczor-Retman) - selftests/lam: Move cpu_has_la57() to use cpuinfo flag - selftests/lam: Skip test if LAM is disabled - selftests/lam: Test get_user() LAM pointer handling AMD SMN access updates: - Add SMN offsets to exclusive region access (Mario Limonciello) - Add support for debugfs access to SMN registers (Mario Limonciello) - Have HSMP use SMN through AMD_NODE (Yazen Ghannam) Power management updates: (Patryk Wlazlyn) - Allow calling mwait_play_dead with an arbitrary hint - ACPI/processor_idle: Add FFH state handling - intel_idle: Provide the default enter_dead() handler - Eliminate mwait_play_dead_cpuid_hint() Bootup: Build system: - Raise the minimum GCC version to 8.1 (Brian Gerst) - Raise the minimum LLVM version to 15.0.0 (Nathan Chancellor) Kconfig: (Arnd Bergmann) - Add cmpxchg8b support back to Geode CPUs - Drop 32-bit "bigsmp" machine support - Rework CONFIG_GENERIC_CPU compiler flags - Drop configuration options for early 64-bit CPUs - Remove CONFIG_HIGHMEM64G support - Drop CONFIG_SWIOTLB for PAE - Drop support for CONFIG_HIGHPTE - Document CONFIG_X86_INTEL_MID as 64-bit-only - Remove old STA2x11 support - Only allow CONFIG_EISA for 32-bit Headers: - Replace __ASSEMBLY__ with __ASSEMBLER__ in UAPI and non-UAPI headers (Thomas Huth) Assembly code & machine code patching: - x86/alternatives: Simplify alternative_call() interface (Josh Poimboeuf) - x86/alternatives: Simplify callthunk patching (Peter Zijlstra) - KVM: VMX: Use named operands in inline asm (Josh Poimboeuf) - x86/hyperv: Use named operands in inline asm (Josh Poimboeuf) - x86/traps: Cleanup and robustify decode_bug() (Peter Zijlstra) - x86/kexec: Merge x86_32 and x86_64 code using macros from <asm/asm.h> (Uros Bizjak) - Use named operands in inline asm (Uros Bizjak) - Improve performance by using asm_inline() for atomic locking instructions (Uros Bizjak) Earlyprintk: - Harden early_serial (Peter Zijlstra) NMI handler: - Add an emergency handler in nmi_desc & use it in nmi_shootdown_cpus() (Waiman Long) Miscellaneous fixes and cleanups: - by Ahmed S. Darwish, Andy Shevchenko, Ard Biesheuvel, Artem Bityutskiy, Borislav Petkov, Brendan Jackman, Brian Gerst, Dan Carpenter, Dr. David Alan Gilbert, H. Peter Anvin, Ingo Molnar, Josh Poimboeuf, Kevin Brodsky, Mike Rapoport, Lukas Bulwahn, Maciej Wieczor-Retman, Max Grobecker, Patryk Wlazlyn, Pawan Gupta, Peter Zijlstra, Philip Redkin, Qasim Ijaz, Rik van Riel, Thomas Gleixner, Thorsten Blum, Tom Lendacky, Tony Luck, Uros Bizjak, Vitaly Kuznetsov, Xin Li, liuye. Signed-off-by: Ingo Molnar <mingo@kernel.org> -----BEGIN PGP SIGNATURE----- iQJFBAABCgAvFiEEBpT5eoXrXCwVQwEKEnMQ0APhK1gFAmfenkQRHG1pbmdvQGtl cm5lbC5vcmcACgkQEnMQ0APhK1g1FRAAi6OFTSn/5aeLMI0IMNBxJ6ddQiFc3imd 7+C/vU5nul4CyDs8mKyj/+f/DDrbkG9lKz3VG631Yl237lXHjD8XWcVMeC/1z/q0 3zInDIloE9/nBHRPkF6F7fARBLBZ0LFgaBsGrCo7mwpGybiQdqGcqcxllvTbtXaw OHta4q6ok+lBDNlfc0v6H4cRnzhmmlKu6Ng0j6UI3V7uFhi3vtxas32ltDQtzorq 2+jbV6/+kbrrv+xPC+jlzOFhTEKRupNPQXmvyQteoQg6G3kqAKMDvBthGXd1rHuX Qa+BoDIifE/2NiVeRwNrhoqYH/pHCzUzDREW5IW8+ca+4XNKuzAC6EuC8CeCzyK1 q8ZjZjooQW4zEeVFeJYllHONzJYfxfSH5CLsnbcuhq99yfGlrQhF1qL72/Omn1w/ DfPJM8Zt5zyKvLqUg3Md+fkVCO2wyDNhB61QPzRgHF+yD+rvuDpoqvUWir+w7cSn fwEDVZGXlFx6dumtSrqRaTd1nvFt80s8yP2ll09DMvGQ8D/yruS7hndGAmmJVCSW NAfd8pSjq5v2+ux2UR92/Cc3VF3SjaUqHBOp/Nq9rESya18ZVa3cJpHhVYYtPIVf THW0h07RIkGVKs1uq+5ekLCr/8uAZg58UPIqmhTuW0ttymRHCNfohR45FQZzy+0M tJj1oc2TIZw= =Dcb3 -----END PGP SIGNATURE----- Merge tag 'x86-core-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull core x86 updates from Ingo Molnar: "x86 CPU features support: - Generate the <asm/cpufeaturemasks.h> header based on build config (H. Peter Anvin, Xin Li) - x86 CPUID parsing updates and fixes (Ahmed S. Darwish) - Introduce the 'setcpuid=' boot parameter (Brendan Jackman) - Enable modifying CPU bug flags with '{clear,set}puid=' (Brendan Jackman) - Utilize CPU-type for CPU matching (Pawan Gupta) - Warn about unmet CPU feature dependencies (Sohil Mehta) - Prepare for new Intel Family numbers (Sohil Mehta) Percpu code: - Standardize & reorganize the x86 percpu layout and related cleanups (Brian Gerst) - Convert the stackprotector canary to a regular percpu variable (Brian Gerst) - Add a percpu subsection for cache hot data (Brian Gerst) - Unify __pcpu_op{1,2}_N() macros to __pcpu_op_N() (Uros Bizjak) - Construct __percpu_seg_override from __percpu_seg (Uros Bizjak) MM: - Add support for broadcast TLB invalidation using AMD's INVLPGB instruction (Rik van Riel) - Rework ROX cache to avoid writable copy (Mike Rapoport) - PAT: restore large ROX pages after fragmentation (Kirill A. Shutemov, Mike Rapoport) - Make memremap(MEMREMAP_WB) map memory as encrypted by default (Kirill A. Shutemov) - Robustify page table initialization (Kirill A. Shutemov) - Fix flush_tlb_range() when used for zapping normal PMDs (Jann Horn) - Clear _PAGE_DIRTY for kernel mappings when we clear _PAGE_RW (Matthew Wilcox) KASLR: - x86/kaslr: Reduce KASLR entropy on most x86 systems, to support PCI BAR space beyond the 10TiB region (CONFIG_PCI_P2PDMA=y) (Balbir Singh) CPU bugs: - Implement FineIBT-BHI mitigation (Peter Zijlstra) - speculation: Simplify and make CALL_NOSPEC consistent (Pawan Gupta) - speculation: Add a conditional CS prefix to CALL_NOSPEC (Pawan Gupta) - RFDS: Exclude P-only parts from the RFDS affected list (Pawan Gupta) System calls: - Break up entry/common.c (Brian Gerst) - Move sysctls into arch/x86 (Joel Granados) Intel LAM support updates: (Maciej Wieczor-Retman) - selftests/lam: Move cpu_has_la57() to use cpuinfo flag - selftests/lam: Skip test if LAM is disabled - selftests/lam: Test get_user() LAM pointer handling AMD SMN access updates: - Add SMN offsets to exclusive region access (Mario Limonciello) - Add support for debugfs access to SMN registers (Mario Limonciello) - Have HSMP use SMN through AMD_NODE (Yazen Ghannam) Power management updates: (Patryk Wlazlyn) - Allow calling mwait_play_dead with an arbitrary hint - ACPI/processor_idle: Add FFH state handling - intel_idle: Provide the default enter_dead() handler - Eliminate mwait_play_dead_cpuid_hint() Build system: - Raise the minimum GCC version to 8.1 (Brian Gerst) - Raise the minimum LLVM version to 15.0.0 (Nathan Chancellor) Kconfig: (Arnd Bergmann) - Add cmpxchg8b support back to Geode CPUs - Drop 32-bit "bigsmp" machine support - Rework CONFIG_GENERIC_CPU compiler flags - Drop configuration options for early 64-bit CPUs - Remove CONFIG_HIGHMEM64G support - Drop CONFIG_SWIOTLB for PAE - Drop support for CONFIG_HIGHPTE - Document CONFIG_X86_INTEL_MID as 64-bit-only - Remove old STA2x11 support - Only allow CONFIG_EISA for 32-bit Headers: - Replace __ASSEMBLY__ with __ASSEMBLER__ in UAPI and non-UAPI headers (Thomas Huth) Assembly code & machine code patching: - x86/alternatives: Simplify alternative_call() interface (Josh Poimboeuf) - x86/alternatives: Simplify callthunk patching (Peter Zijlstra) - KVM: VMX: Use named operands in inline asm (Josh Poimboeuf) - x86/hyperv: Use named operands in inline asm (Josh Poimboeuf) - x86/traps: Cleanup and robustify decode_bug() (Peter Zijlstra) - x86/kexec: Merge x86_32 and x86_64 code using macros from <asm/asm.h> (Uros Bizjak) - Use named operands in inline asm (Uros Bizjak) - Improve performance by using asm_inline() for atomic locking instructions (Uros Bizjak) Earlyprintk: - Harden early_serial (Peter Zijlstra) NMI handler: - Add an emergency handler in nmi_desc & use it in nmi_shootdown_cpus() (Waiman Long) Miscellaneous fixes and cleanups: - by Ahmed S. Darwish, Andy Shevchenko, Ard Biesheuvel, Artem Bityutskiy, Borislav Petkov, Brendan Jackman, Brian Gerst, Dan Carpenter, Dr. David Alan Gilbert, H. Peter Anvin, Ingo Molnar, Josh Poimboeuf, Kevin Brodsky, Mike Rapoport, Lukas Bulwahn, Maciej Wieczor-Retman, Max Grobecker, Patryk Wlazlyn, Pawan Gupta, Peter Zijlstra, Philip Redkin, Qasim Ijaz, Rik van Riel, Thomas Gleixner, Thorsten Blum, Tom Lendacky, Tony Luck, Uros Bizjak, Vitaly Kuznetsov, Xin Li, liuye" * tag 'x86-core-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (211 commits) zstd: Increase DYNAMIC_BMI2 GCC version cutoff from 4.8 to 11.0 to work around compiler segfault x86/asm: Make asm export of __ref_stack_chk_guard unconditional x86/mm: Only do broadcast flush from reclaim if pages were unmapped perf/x86/intel, x86/cpu: Replace Pentium 4 model checks with VFM ones perf/x86/intel, x86/cpu: Simplify Intel PMU initialization x86/headers: Replace __ASSEMBLY__ with __ASSEMBLER__ in non-UAPI headers x86/headers: Replace __ASSEMBLY__ with __ASSEMBLER__ in UAPI headers x86/locking/atomic: Improve performance by using asm_inline() for atomic locking instructions x86/asm: Use asm_inline() instead of asm() in clwb() x86/asm: Use CLFLUSHOPT and CLWB mnemonics in <asm/special_insns.h> x86/hweight: Use asm_inline() instead of asm() x86/hweight: Use ASM_CALL_CONSTRAINT in inline asm() x86/hweight: Use named operands in inline asm() x86/stackprotector/64: Only export __ref_stack_chk_guard on CONFIG_SMP x86/head/64: Avoid Clang < 17 stack protector in startup code x86/kexec: Merge x86_32 and x86_64 code using macros from <asm/asm.h> x86/runtime-const: Add the RUNTIME_CONST_PTR assembly macro x86/cpu/intel: Limit the non-architectural constant_tsc model checks x86/mm/pat: Replace Intel x86_model checks with VFM ones x86/cpu/intel: Fix fast string initialization for extended Families ...
589 lines
17 KiB
C
589 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* prepare to run common code
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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*/
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/* cpu_feature_enabled() cannot be used this early */
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#define USE_EARLY_PGTABLE_L5
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/percpu.h>
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#include <linux/start_kernel.h>
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#include <linux/io.h>
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#include <linux/memblock.h>
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#include <linux/cc_platform.h>
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#include <linux/pgtable.h>
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#include <asm/asm.h>
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#include <asm/page_64.h>
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#include <asm/processor.h>
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#include <asm/proto.h>
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#include <asm/smp.h>
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#include <asm/setup.h>
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#include <asm/desc.h>
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#include <asm/tlbflush.h>
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#include <asm/sections.h>
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#include <asm/kdebug.h>
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#include <asm/e820/api.h>
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#include <asm/bios_ebda.h>
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#include <asm/bootparam_utils.h>
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#include <asm/microcode.h>
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#include <asm/kasan.h>
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#include <asm/fixmap.h>
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#include <asm/realmode.h>
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#include <asm/extable.h>
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#include <asm/trapnr.h>
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#include <asm/sev.h>
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#include <asm/tdx.h>
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#include <asm/init.h>
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/*
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* Manage page tables very early on.
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*/
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extern pmd_t early_dynamic_pgts[EARLY_DYNAMIC_PAGE_TABLES][PTRS_PER_PMD];
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static unsigned int __initdata next_early_pgt;
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pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
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#ifdef CONFIG_X86_5LEVEL
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unsigned int __pgtable_l5_enabled __ro_after_init;
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unsigned int pgdir_shift __ro_after_init = 39;
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EXPORT_SYMBOL(pgdir_shift);
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unsigned int ptrs_per_p4d __ro_after_init = 1;
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EXPORT_SYMBOL(ptrs_per_p4d);
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#endif
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#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
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unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
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EXPORT_SYMBOL(page_offset_base);
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unsigned long vmalloc_base __ro_after_init = __VMALLOC_BASE_L4;
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EXPORT_SYMBOL(vmalloc_base);
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unsigned long vmemmap_base __ro_after_init = __VMEMMAP_BASE_L4;
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EXPORT_SYMBOL(vmemmap_base);
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#endif
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static inline bool check_la57_support(void)
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{
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if (!IS_ENABLED(CONFIG_X86_5LEVEL))
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return false;
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/*
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* 5-level paging is detected and enabled at kernel decompression
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* stage. Only check if it has been enabled there.
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*/
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if (!(native_read_cr4() & X86_CR4_LA57))
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return false;
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RIP_REL_REF(__pgtable_l5_enabled) = 1;
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RIP_REL_REF(pgdir_shift) = 48;
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RIP_REL_REF(ptrs_per_p4d) = 512;
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RIP_REL_REF(page_offset_base) = __PAGE_OFFSET_BASE_L5;
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RIP_REL_REF(vmalloc_base) = __VMALLOC_BASE_L5;
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RIP_REL_REF(vmemmap_base) = __VMEMMAP_BASE_L5;
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return true;
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}
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static unsigned long __head sme_postprocess_startup(struct boot_params *bp,
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pmdval_t *pmd,
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unsigned long p2v_offset)
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{
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unsigned long paddr, paddr_end;
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int i;
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/* Encrypt the kernel and related (if SME is active) */
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sme_encrypt_kernel(bp);
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/*
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* Clear the memory encryption mask from the .bss..decrypted section.
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* The bss section will be memset to zero later in the initialization so
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* there is no need to zero it after changing the memory encryption
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* attribute.
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*/
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if (sme_get_me_mask()) {
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paddr = (unsigned long)&RIP_REL_REF(__start_bss_decrypted);
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paddr_end = (unsigned long)&RIP_REL_REF(__end_bss_decrypted);
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for (; paddr < paddr_end; paddr += PMD_SIZE) {
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/*
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* On SNP, transition the page to shared in the RMP table so that
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* it is consistent with the page table attribute change.
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*
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* __start_bss_decrypted has a virtual address in the high range
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* mapping (kernel .text). PVALIDATE, by way of
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* early_snp_set_memory_shared(), requires a valid virtual
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* address but the kernel is currently running off of the identity
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* mapping so use the PA to get a *currently* valid virtual address.
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*/
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early_snp_set_memory_shared(paddr, paddr, PTRS_PER_PMD);
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i = pmd_index(paddr - p2v_offset);
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pmd[i] -= sme_get_me_mask();
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}
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}
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/*
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* Return the SME encryption mask (if SME is active) to be used as a
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* modifier for the initial pgdir entry programmed into CR3.
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*/
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return sme_get_me_mask();
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}
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/* Code in __startup_64() can be relocated during execution, but the compiler
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* doesn't have to generate PC-relative relocations when accessing globals from
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* that function. Clang actually does not generate them, which leads to
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* boot-time crashes. To work around this problem, every global pointer must
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* be accessed using RIP_REL_REF(). Kernel virtual addresses can be determined
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* by subtracting p2v_offset from the RIP-relative address.
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*/
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unsigned long __head __startup_64(unsigned long p2v_offset,
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struct boot_params *bp)
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{
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pmd_t (*early_pgts)[PTRS_PER_PMD] = RIP_REL_REF(early_dynamic_pgts);
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unsigned long physaddr = (unsigned long)&RIP_REL_REF(_text);
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unsigned long va_text, va_end;
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unsigned long pgtable_flags;
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unsigned long load_delta;
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pgdval_t *pgd;
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p4dval_t *p4d;
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pudval_t *pud;
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pmdval_t *pmd, pmd_entry;
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bool la57;
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int i;
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la57 = check_la57_support();
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/* Is the address too large? */
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if (physaddr >> MAX_PHYSMEM_BITS)
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for (;;);
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/*
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* Compute the delta between the address I am compiled to run at
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* and the address I am actually running at.
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*/
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load_delta = __START_KERNEL_map + p2v_offset;
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RIP_REL_REF(phys_base) = load_delta;
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/* Is the address not 2M aligned? */
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if (load_delta & ~PMD_MASK)
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for (;;);
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va_text = physaddr - p2v_offset;
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va_end = (unsigned long)&RIP_REL_REF(_end) - p2v_offset;
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/* Include the SME encryption mask in the fixup value */
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load_delta += sme_get_me_mask();
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/* Fixup the physical addresses in the page table */
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pgd = &RIP_REL_REF(early_top_pgt)->pgd;
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pgd[pgd_index(__START_KERNEL_map)] += load_delta;
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if (IS_ENABLED(CONFIG_X86_5LEVEL) && la57) {
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p4d = (p4dval_t *)&RIP_REL_REF(level4_kernel_pgt);
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p4d[MAX_PTRS_PER_P4D - 1] += load_delta;
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pgd[pgd_index(__START_KERNEL_map)] = (pgdval_t)p4d | _PAGE_TABLE;
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}
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RIP_REL_REF(level3_kernel_pgt)[PTRS_PER_PUD - 2].pud += load_delta;
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RIP_REL_REF(level3_kernel_pgt)[PTRS_PER_PUD - 1].pud += load_delta;
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for (i = FIXMAP_PMD_TOP; i > FIXMAP_PMD_TOP - FIXMAP_PMD_NUM; i--)
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RIP_REL_REF(level2_fixmap_pgt)[i].pmd += load_delta;
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/*
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* Set up the identity mapping for the switchover. These
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* entries should *NOT* have the global bit set! This also
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* creates a bunch of nonsense entries but that is fine --
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* it avoids problems around wraparound.
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*/
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pud = &early_pgts[0]->pmd;
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pmd = &early_pgts[1]->pmd;
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RIP_REL_REF(next_early_pgt) = 2;
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pgtable_flags = _KERNPG_TABLE_NOENC + sme_get_me_mask();
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if (la57) {
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p4d = &early_pgts[RIP_REL_REF(next_early_pgt)++]->pmd;
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i = (physaddr >> PGDIR_SHIFT) % PTRS_PER_PGD;
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pgd[i + 0] = (pgdval_t)p4d + pgtable_flags;
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pgd[i + 1] = (pgdval_t)p4d + pgtable_flags;
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i = physaddr >> P4D_SHIFT;
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p4d[(i + 0) % PTRS_PER_P4D] = (pgdval_t)pud + pgtable_flags;
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p4d[(i + 1) % PTRS_PER_P4D] = (pgdval_t)pud + pgtable_flags;
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} else {
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i = (physaddr >> PGDIR_SHIFT) % PTRS_PER_PGD;
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pgd[i + 0] = (pgdval_t)pud + pgtable_flags;
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pgd[i + 1] = (pgdval_t)pud + pgtable_flags;
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}
|
|
|
|
i = physaddr >> PUD_SHIFT;
|
|
pud[(i + 0) % PTRS_PER_PUD] = (pudval_t)pmd + pgtable_flags;
|
|
pud[(i + 1) % PTRS_PER_PUD] = (pudval_t)pmd + pgtable_flags;
|
|
|
|
pmd_entry = __PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL;
|
|
/* Filter out unsupported __PAGE_KERNEL_* bits: */
|
|
pmd_entry &= RIP_REL_REF(__supported_pte_mask);
|
|
pmd_entry += sme_get_me_mask();
|
|
pmd_entry += physaddr;
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(va_end - va_text, PMD_SIZE); i++) {
|
|
int idx = i + (physaddr >> PMD_SHIFT);
|
|
|
|
pmd[idx % PTRS_PER_PMD] = pmd_entry + i * PMD_SIZE;
|
|
}
|
|
|
|
/*
|
|
* Fixup the kernel text+data virtual addresses. Note that
|
|
* we might write invalid pmds, when the kernel is relocated
|
|
* cleanup_highmap() fixes this up along with the mappings
|
|
* beyond _end.
|
|
*
|
|
* Only the region occupied by the kernel image has so far
|
|
* been checked against the table of usable memory regions
|
|
* provided by the firmware, so invalidate pages outside that
|
|
* region. A page table entry that maps to a reserved area of
|
|
* memory would allow processor speculation into that area,
|
|
* and on some hardware (particularly the UV platform) even
|
|
* speculative access to some reserved areas is caught as an
|
|
* error, causing the BIOS to halt the system.
|
|
*/
|
|
|
|
pmd = &RIP_REL_REF(level2_kernel_pgt)->pmd;
|
|
|
|
/* invalidate pages before the kernel image */
|
|
for (i = 0; i < pmd_index(va_text); i++)
|
|
pmd[i] &= ~_PAGE_PRESENT;
|
|
|
|
/* fixup pages that are part of the kernel image */
|
|
for (; i <= pmd_index(va_end); i++)
|
|
if (pmd[i] & _PAGE_PRESENT)
|
|
pmd[i] += load_delta;
|
|
|
|
/* invalidate pages after the kernel image */
|
|
for (; i < PTRS_PER_PMD; i++)
|
|
pmd[i] &= ~_PAGE_PRESENT;
|
|
|
|
return sme_postprocess_startup(bp, pmd, p2v_offset);
|
|
}
|
|
|
|
/* Wipe all early page tables except for the kernel symbol map */
|
|
static void __init reset_early_page_tables(void)
|
|
{
|
|
memset(early_top_pgt, 0, sizeof(pgd_t)*(PTRS_PER_PGD-1));
|
|
next_early_pgt = 0;
|
|
write_cr3(__sme_pa_nodebug(early_top_pgt));
|
|
}
|
|
|
|
/* Create a new PMD entry */
|
|
bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd)
|
|
{
|
|
unsigned long physaddr = address - __PAGE_OFFSET;
|
|
pgdval_t pgd, *pgd_p;
|
|
p4dval_t p4d, *p4d_p;
|
|
pudval_t pud, *pud_p;
|
|
pmdval_t *pmd_p;
|
|
|
|
/* Invalid address or early pgt is done ? */
|
|
if (physaddr >= MAXMEM || read_cr3_pa() != __pa_nodebug(early_top_pgt))
|
|
return false;
|
|
|
|
again:
|
|
pgd_p = &early_top_pgt[pgd_index(address)].pgd;
|
|
pgd = *pgd_p;
|
|
|
|
/*
|
|
* The use of __START_KERNEL_map rather than __PAGE_OFFSET here is
|
|
* critical -- __PAGE_OFFSET would point us back into the dynamic
|
|
* range and we might end up looping forever...
|
|
*/
|
|
if (!pgtable_l5_enabled())
|
|
p4d_p = pgd_p;
|
|
else if (pgd)
|
|
p4d_p = (p4dval_t *)((pgd & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
|
|
else {
|
|
if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
|
|
reset_early_page_tables();
|
|
goto again;
|
|
}
|
|
|
|
p4d_p = (p4dval_t *)early_dynamic_pgts[next_early_pgt++];
|
|
memset(p4d_p, 0, sizeof(*p4d_p) * PTRS_PER_P4D);
|
|
*pgd_p = (pgdval_t)p4d_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
|
|
}
|
|
p4d_p += p4d_index(address);
|
|
p4d = *p4d_p;
|
|
|
|
if (p4d)
|
|
pud_p = (pudval_t *)((p4d & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
|
|
else {
|
|
if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
|
|
reset_early_page_tables();
|
|
goto again;
|
|
}
|
|
|
|
pud_p = (pudval_t *)early_dynamic_pgts[next_early_pgt++];
|
|
memset(pud_p, 0, sizeof(*pud_p) * PTRS_PER_PUD);
|
|
*p4d_p = (p4dval_t)pud_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
|
|
}
|
|
pud_p += pud_index(address);
|
|
pud = *pud_p;
|
|
|
|
if (pud)
|
|
pmd_p = (pmdval_t *)((pud & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
|
|
else {
|
|
if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
|
|
reset_early_page_tables();
|
|
goto again;
|
|
}
|
|
|
|
pmd_p = (pmdval_t *)early_dynamic_pgts[next_early_pgt++];
|
|
memset(pmd_p, 0, sizeof(*pmd_p) * PTRS_PER_PMD);
|
|
*pud_p = (pudval_t)pmd_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
|
|
}
|
|
pmd_p[pmd_index(address)] = pmd;
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool __init early_make_pgtable(unsigned long address)
|
|
{
|
|
unsigned long physaddr = address - __PAGE_OFFSET;
|
|
pmdval_t pmd;
|
|
|
|
pmd = (physaddr & PMD_MASK) + early_pmd_flags;
|
|
|
|
return __early_make_pgtable(address, pmd);
|
|
}
|
|
|
|
void __init do_early_exception(struct pt_regs *regs, int trapnr)
|
|
{
|
|
if (trapnr == X86_TRAP_PF &&
|
|
early_make_pgtable(native_read_cr2()))
|
|
return;
|
|
|
|
if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT) &&
|
|
trapnr == X86_TRAP_VC && handle_vc_boot_ghcb(regs))
|
|
return;
|
|
|
|
if (trapnr == X86_TRAP_VE && tdx_early_handle_ve(regs))
|
|
return;
|
|
|
|
early_fixup_exception(regs, trapnr);
|
|
}
|
|
|
|
/* Don't add a printk in there. printk relies on the PDA which is not initialized
|
|
yet. */
|
|
void __init clear_bss(void)
|
|
{
|
|
memset(__bss_start, 0,
|
|
(unsigned long) __bss_stop - (unsigned long) __bss_start);
|
|
memset(__brk_base, 0,
|
|
(unsigned long) __brk_limit - (unsigned long) __brk_base);
|
|
}
|
|
|
|
static unsigned long get_cmd_line_ptr(void)
|
|
{
|
|
unsigned long cmd_line_ptr = boot_params.hdr.cmd_line_ptr;
|
|
|
|
cmd_line_ptr |= (u64)boot_params.ext_cmd_line_ptr << 32;
|
|
|
|
return cmd_line_ptr;
|
|
}
|
|
|
|
static void __init copy_bootdata(char *real_mode_data)
|
|
{
|
|
char * command_line;
|
|
unsigned long cmd_line_ptr;
|
|
|
|
/*
|
|
* If SME is active, this will create decrypted mappings of the
|
|
* boot data in advance of the copy operations.
|
|
*/
|
|
sme_map_bootdata(real_mode_data);
|
|
|
|
memcpy(&boot_params, real_mode_data, sizeof(boot_params));
|
|
sanitize_boot_params(&boot_params);
|
|
cmd_line_ptr = get_cmd_line_ptr();
|
|
if (cmd_line_ptr) {
|
|
command_line = __va(cmd_line_ptr);
|
|
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
|
|
}
|
|
|
|
/*
|
|
* The old boot data is no longer needed and won't be reserved,
|
|
* freeing up that memory for use by the system. If SME is active,
|
|
* we need to remove the mappings that were created so that the
|
|
* memory doesn't remain mapped as decrypted.
|
|
*/
|
|
sme_unmap_bootdata(real_mode_data);
|
|
}
|
|
|
|
asmlinkage __visible void __init __noreturn x86_64_start_kernel(char * real_mode_data)
|
|
{
|
|
/*
|
|
* Build-time sanity checks on the kernel image and module
|
|
* area mappings. (these are purely build-time and produce no code)
|
|
*/
|
|
BUILD_BUG_ON(MODULES_VADDR < __START_KERNEL_map);
|
|
BUILD_BUG_ON(MODULES_VADDR - __START_KERNEL_map < KERNEL_IMAGE_SIZE);
|
|
BUILD_BUG_ON(MODULES_LEN + KERNEL_IMAGE_SIZE > 2*PUD_SIZE);
|
|
BUILD_BUG_ON((__START_KERNEL_map & ~PMD_MASK) != 0);
|
|
BUILD_BUG_ON((MODULES_VADDR & ~PMD_MASK) != 0);
|
|
BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL));
|
|
MAYBE_BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
|
|
(__START_KERNEL & PGDIR_MASK)));
|
|
BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) <= MODULES_END);
|
|
|
|
cr4_init_shadow();
|
|
|
|
/* Kill off the identity-map trampoline */
|
|
reset_early_page_tables();
|
|
|
|
clear_bss();
|
|
|
|
/*
|
|
* This needs to happen *before* kasan_early_init() because latter maps stuff
|
|
* into that page.
|
|
*/
|
|
clear_page(init_top_pgt);
|
|
|
|
/*
|
|
* SME support may update early_pmd_flags to include the memory
|
|
* encryption mask, so it needs to be called before anything
|
|
* that may generate a page fault.
|
|
*/
|
|
sme_early_init();
|
|
|
|
kasan_early_init();
|
|
|
|
/*
|
|
* Flush global TLB entries which could be left over from the trampoline page
|
|
* table.
|
|
*
|
|
* This needs to happen *after* kasan_early_init() as KASAN-enabled .configs
|
|
* instrument native_write_cr4() so KASAN must be initialized for that
|
|
* instrumentation to work.
|
|
*/
|
|
__native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4));
|
|
|
|
idt_setup_early_handler();
|
|
|
|
/* Needed before cc_platform_has() can be used for TDX */
|
|
tdx_early_init();
|
|
|
|
copy_bootdata(__va(real_mode_data));
|
|
|
|
/*
|
|
* Load microcode early on BSP.
|
|
*/
|
|
load_ucode_bsp();
|
|
|
|
/* set init_top_pgt kernel high mapping*/
|
|
init_top_pgt[511] = early_top_pgt[511];
|
|
|
|
x86_64_start_reservations(real_mode_data);
|
|
}
|
|
|
|
void __init __noreturn x86_64_start_reservations(char *real_mode_data)
|
|
{
|
|
/* version is always not zero if it is copied */
|
|
if (!boot_params.hdr.version)
|
|
copy_bootdata(__va(real_mode_data));
|
|
|
|
x86_early_init_platform_quirks();
|
|
|
|
switch (boot_params.hdr.hardware_subarch) {
|
|
case X86_SUBARCH_INTEL_MID:
|
|
x86_intel_mid_early_setup();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
start_kernel();
|
|
}
|
|
|
|
/*
|
|
* Data structures and code used for IDT setup in head_64.S. The bringup-IDT is
|
|
* used until the idt_table takes over. On the boot CPU this happens in
|
|
* x86_64_start_kernel(), on secondary CPUs in start_secondary(). In both cases
|
|
* this happens in the functions called from head_64.S.
|
|
*
|
|
* The idt_table can't be used that early because all the code modifying it is
|
|
* in idt.c and can be instrumented by tracing or KASAN, which both don't work
|
|
* during early CPU bringup. Also the idt_table has the runtime vectors
|
|
* configured which require certain CPU state to be setup already (like TSS),
|
|
* which also hasn't happened yet in early CPU bringup.
|
|
*/
|
|
static gate_desc bringup_idt_table[NUM_EXCEPTION_VECTORS] __page_aligned_data;
|
|
|
|
/* This may run while still in the direct mapping */
|
|
static void __head startup_64_load_idt(void *vc_handler)
|
|
{
|
|
struct desc_ptr desc = {
|
|
.address = (unsigned long)&RIP_REL_REF(bringup_idt_table),
|
|
.size = sizeof(bringup_idt_table) - 1,
|
|
};
|
|
struct idt_data data;
|
|
gate_desc idt_desc;
|
|
|
|
/* @vc_handler is set only for a VMM Communication Exception */
|
|
if (vc_handler) {
|
|
init_idt_data(&data, X86_TRAP_VC, vc_handler);
|
|
idt_init_desc(&idt_desc, &data);
|
|
native_write_idt_entry((gate_desc *)desc.address, X86_TRAP_VC, &idt_desc);
|
|
}
|
|
|
|
native_load_idt(&desc);
|
|
}
|
|
|
|
/* This is used when running on kernel addresses */
|
|
void early_setup_idt(void)
|
|
{
|
|
void *handler = NULL;
|
|
|
|
if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) {
|
|
setup_ghcb();
|
|
handler = vc_boot_ghcb;
|
|
}
|
|
|
|
startup_64_load_idt(handler);
|
|
}
|
|
|
|
/*
|
|
* Setup boot CPU state needed before kernel switches to virtual addresses.
|
|
*/
|
|
void __head startup_64_setup_gdt_idt(void)
|
|
{
|
|
struct desc_struct *gdt = (void *)(__force unsigned long)gdt_page.gdt;
|
|
void *handler = NULL;
|
|
|
|
struct desc_ptr startup_gdt_descr = {
|
|
.address = (unsigned long)&RIP_REL_REF(*gdt),
|
|
.size = GDT_SIZE - 1,
|
|
};
|
|
|
|
/* Load GDT */
|
|
native_load_gdt(&startup_gdt_descr);
|
|
|
|
/* New GDT is live - reload data segment registers */
|
|
asm volatile("movl %%eax, %%ds\n"
|
|
"movl %%eax, %%ss\n"
|
|
"movl %%eax, %%es\n" : : "a"(__KERNEL_DS) : "memory");
|
|
|
|
if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT))
|
|
handler = &RIP_REL_REF(vc_no_ghcb);
|
|
|
|
startup_64_load_idt(handler);
|
|
}
|