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4d69529812
Add clock and reset entries for the Renesas RZ/V2H(P) DMAC IPs. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250220150110.738619-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
310 lines
11 KiB
C
310 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/V2H(P) CPG driver
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
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#include "rzv2h-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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CLK_RTXIN,
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CLK_QEXTAL,
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/* PLL Clocks */
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CLK_PLLCM33,
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CLK_PLLCLN,
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CLK_PLLDTY,
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CLK_PLLCA55,
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CLK_PLLVDO,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV4,
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CLK_PLLCM33_DIV4_PLLCM33,
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CLK_PLLCM33_DIV16,
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CLK_PLLCLN_DIV2,
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CLK_PLLCLN_DIV8,
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CLK_PLLCLN_DIV16,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV2,
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CLK_PLLDTY_ACPU_DIV4,
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CLK_PLLDTY_DIV16,
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CLK_PLLDTY_RCPU,
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CLK_PLLDTY_RCPU_DIV4,
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CLK_PLLVDO_CRU0,
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CLK_PLLVDO_CRU1,
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CLK_PLLVDO_CRU2,
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CLK_PLLVDO_CRU3,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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static const struct clk_div_table dtable_1_8[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_4[] = {
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{0, 2},
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{1, 4},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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{2, 8},
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{3, 16},
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{4, 64},
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{0, 0},
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};
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static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
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DEF_INPUT("rtxin", CLK_RTXIN),
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DEF_INPUT("qextal", CLK_QEXTAL),
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/* PLL Clocks */
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
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DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
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DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33,
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CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
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DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
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DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
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DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
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DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
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DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
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DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
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DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
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DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
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DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55,
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CDDIV1_DIVCTL0, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55,
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CDDIV1_DIVCTL1, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55,
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CDDIV1_DIVCTL2, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55,
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CDDIV1_DIVCTL3, dtable_1_8),
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DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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};
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static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
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DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0,
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BUS_MSTOP(5, BIT(9))),
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DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
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BUS_MSTOP(3, BIT(2))),
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DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
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BUS_MSTOP(3, BIT(3))),
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DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
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BUS_MSTOP(10, BIT(11))),
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DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
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BUS_MSTOP(10, BIT(12))),
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DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
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BUS_MSTOP_NONE),
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DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
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BUS_MSTOP(3, BIT(5))),
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DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
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BUS_MSTOP(5, BIT(10))),
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DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
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BUS_MSTOP(5, BIT(11))),
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DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
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BUS_MSTOP(2, BIT(13))),
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DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
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BUS_MSTOP(2, BIT(14))),
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DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
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BUS_MSTOP(11, BIT(13))),
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DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
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BUS_MSTOP(11, BIT(14))),
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DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
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BUS_MSTOP(11, BIT(15))),
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DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
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BUS_MSTOP(12, BIT(0))),
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DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
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BUS_MSTOP(3, BIT(10))),
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DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
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BUS_MSTOP(3, BIT(10))),
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DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
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BUS_MSTOP(1, BIT(0))),
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DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
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BUS_MSTOP(1, BIT(0))),
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DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
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BUS_MSTOP(5, BIT(12))),
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DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
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BUS_MSTOP(5, BIT(12))),
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DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
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BUS_MSTOP(3, BIT(13))),
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DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
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BUS_MSTOP(1, BIT(1))),
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DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
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BUS_MSTOP(1, BIT(2))),
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DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
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BUS_MSTOP(1, BIT(3))),
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DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
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BUS_MSTOP(1, BIT(4))),
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DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
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BUS_MSTOP(1, BIT(5))),
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DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
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BUS_MSTOP(1, BIT(6))),
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DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
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BUS_MSTOP(1, BIT(7))),
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DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
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BUS_MSTOP(1, BIT(8))),
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DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
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BUS_MSTOP(9, BIT(5))),
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DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
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BUS_MSTOP(9, BIT(5))),
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DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
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BUS_MSTOP(9, BIT(5))),
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DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
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BUS_MSTOP(9, BIT(6))),
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DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
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BUS_MSTOP(9, BIT(6))),
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DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
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BUS_MSTOP(9, BIT(6))),
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DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
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BUS_MSTOP(9, BIT(7))),
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DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
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BUS_MSTOP(9, BIT(7))),
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DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
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BUS_MSTOP(9, BIT(7))),
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};
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static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
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DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
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DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
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DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
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DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
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DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
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DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
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DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
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DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
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DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
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DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
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DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
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DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
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DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
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DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
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DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
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DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
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DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
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DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
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DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
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DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
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DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
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DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
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DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
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DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
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DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
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DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
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DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
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DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
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DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
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DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
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DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
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DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
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DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
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DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
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DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
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DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
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DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
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DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
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DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
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DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
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DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
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DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
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DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
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};
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const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
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/* Core Clocks */
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.core_clks = r9a09g057_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g057_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r9a09g057_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks),
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.num_hw_mod_clks = 25 * 16,
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/* Resets */
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.resets = r9a09g057_resets,
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.num_resets = ARRAY_SIZE(r9a09g057_resets),
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.num_mstop_bits = 192,
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};
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