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e987e22e92
When the new register addresses were introduced for V3D 7.x, we added
new masks for performance counter sources on V3D 7.x. Nevertheless,
we never apply these new masks when setting the sources.
Fix the performance counter source settings on V3D 7.x by introducing
a new macro, `V3D_SET_FIELD_VER`, which allows fields setting to vary
by version. Using this macro, we can provide different values for
source mask based on the V3D version, ensuring that sources are
correctly configure on V3D 7.x.
Fixes: 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x")
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241106121736.5707-1-mcanal@igalia.com
290 lines
8.4 KiB
C
290 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2014-2018 Broadcom */
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#include <linux/circ_buf.h>
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#include <linux/ctype.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/string_helpers.h>
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#include <drm/drm_debugfs.h>
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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#define REGDEF(min_ver, max_ver, reg) { min_ver, max_ver, reg, #reg }
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struct v3d_reg_def {
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u32 min_ver;
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u32 max_ver;
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u32 reg;
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const char *name;
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};
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static const struct v3d_reg_def v3d_hub_reg_defs[] = {
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REGDEF(33, 42, V3D_HUB_AXICFG),
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REGDEF(33, 71, V3D_HUB_UIFCFG),
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REGDEF(33, 71, V3D_HUB_IDENT0),
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REGDEF(33, 71, V3D_HUB_IDENT1),
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REGDEF(33, 71, V3D_HUB_IDENT2),
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REGDEF(33, 71, V3D_HUB_IDENT3),
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REGDEF(33, 71, V3D_HUB_INT_STS),
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REGDEF(33, 71, V3D_HUB_INT_MSK_STS),
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REGDEF(33, 71, V3D_MMU_CTL),
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REGDEF(33, 71, V3D_MMU_VIO_ADDR),
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REGDEF(33, 71, V3D_MMU_VIO_ID),
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REGDEF(33, 71, V3D_MMU_DEBUG_INFO),
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REGDEF(71, 71, V3D_GMP_STATUS(71)),
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REGDEF(71, 71, V3D_GMP_CFG(71)),
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REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
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};
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static const struct v3d_reg_def v3d_gca_reg_defs[] = {
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REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
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REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
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};
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static const struct v3d_reg_def v3d_core_reg_defs[] = {
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REGDEF(33, 71, V3D_CTL_IDENT0),
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REGDEF(33, 71, V3D_CTL_IDENT1),
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REGDEF(33, 71, V3D_CTL_IDENT2),
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REGDEF(33, 71, V3D_CTL_MISCCFG),
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REGDEF(33, 71, V3D_CTL_INT_STS),
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REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
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REGDEF(33, 71, V3D_CLE_CT0CS),
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REGDEF(33, 71, V3D_CLE_CT0CA),
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REGDEF(33, 71, V3D_CLE_CT0EA),
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REGDEF(33, 71, V3D_CLE_CT1CS),
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REGDEF(33, 71, V3D_CLE_CT1CA),
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REGDEF(33, 71, V3D_CLE_CT1EA),
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REGDEF(33, 71, V3D_PTB_BPCA),
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REGDEF(33, 71, V3D_PTB_BPCS),
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REGDEF(33, 42, V3D_GMP_STATUS(33)),
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REGDEF(33, 42, V3D_GMP_CFG(33)),
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REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),
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REGDEF(33, 71, V3D_ERR_FDBGO),
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REGDEF(33, 71, V3D_ERR_FDBGB),
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REGDEF(33, 71, V3D_ERR_FDBGS),
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REGDEF(33, 71, V3D_ERR_STAT),
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};
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static const struct v3d_reg_def v3d_csd_reg_defs[] = {
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REGDEF(41, 71, V3D_CSD_STATUS),
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REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
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REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
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REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
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REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
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REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
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REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
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REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
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REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
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REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
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REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
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REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
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REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
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REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
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REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
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REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
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};
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static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
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{
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struct drm_debugfs_entry *entry = m->private;
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struct drm_device *dev = entry->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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int i, core;
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for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
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const struct v3d_reg_def *def = &v3d_hub_reg_defs[i];
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if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
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seq_printf(m, "%s (0x%04x): 0x%08x\n",
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def->name, def->reg, V3D_READ(def->reg));
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}
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}
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for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
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const struct v3d_reg_def *def = &v3d_gca_reg_defs[i];
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if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
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seq_printf(m, "%s (0x%04x): 0x%08x\n",
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def->name, def->reg, V3D_GCA_READ(def->reg));
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}
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}
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for (core = 0; core < v3d->cores; core++) {
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for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
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const struct v3d_reg_def *def = &v3d_core_reg_defs[i];
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if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
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seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
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core, def->name, def->reg,
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V3D_CORE_READ(core, def->reg));
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}
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}
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for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
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const struct v3d_reg_def *def = &v3d_csd_reg_defs[i];
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if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
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seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
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core, def->name, def->reg,
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V3D_CORE_READ(core, def->reg));
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}
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}
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}
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return 0;
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}
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static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
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{
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struct drm_debugfs_entry *entry = m->private;
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struct drm_device *dev = entry->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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u32 ident0, ident1, ident2, ident3, cores;
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int core;
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ident0 = V3D_READ(V3D_HUB_IDENT0);
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ident1 = V3D_READ(V3D_HUB_IDENT1);
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ident2 = V3D_READ(V3D_HUB_IDENT2);
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ident3 = V3D_READ(V3D_HUB_IDENT3);
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cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
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seq_printf(m, "Revision: %d.%d.%d.%d\n",
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V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
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V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
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V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
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V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
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seq_printf(m, "MMU: %s\n",
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str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
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seq_printf(m, "TFU: %s\n",
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str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
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if (v3d->ver <= 42) {
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seq_printf(m, "TSY: %s\n",
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str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
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}
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seq_printf(m, "MSO: %s\n",
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str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO));
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seq_printf(m, "L3C: %s (%dkb)\n",
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str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_L3C),
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V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));
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for (core = 0; core < cores; core++) {
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u32 misccfg;
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u32 nslc, ntmu, qups;
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ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
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ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
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ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
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misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);
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nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
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ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
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qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);
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seq_printf(m, "Core %d:\n", core);
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seq_printf(m, " Revision: %d.%d\n",
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V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
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V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
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seq_printf(m, " Slices: %d\n", nslc);
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seq_printf(m, " TMUs: %d\n", nslc * ntmu);
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seq_printf(m, " QPUs: %d\n", nslc * qups);
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seq_printf(m, " Semaphores: %d\n",
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V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
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if (v3d->ver <= 42) {
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seq_printf(m, " BCG int: %d\n",
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(ident2 & V3D_IDENT2_BCG_INT) != 0);
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}
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if (v3d->ver < 40) {
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seq_printf(m, " Override TMU: %d\n",
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(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
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}
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}
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return 0;
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}
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static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused)
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{
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struct drm_debugfs_entry *entry = m->private;
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struct drm_device *dev = entry->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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mutex_lock(&v3d->bo_lock);
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seq_printf(m, "allocated bos: %d\n",
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v3d->bo_stats.num_allocated);
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seq_printf(m, "allocated bo size (kb): %ld\n",
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(long)v3d->bo_stats.pages_allocated << (V3D_MMU_PAGE_SHIFT - 10));
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mutex_unlock(&v3d->bo_lock);
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return 0;
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}
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static int v3d_measure_clock(struct seq_file *m, void *unused)
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{
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struct drm_debugfs_entry *entry = m->private;
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struct drm_device *dev = entry->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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uint32_t cycles;
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int core = 0;
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int measure_ms = 1000;
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if (v3d->ver >= 40) {
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int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver);
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V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
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V3D_SET_FIELD_VER(cycle_count_reg,
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V3D_PCTR_S0, v3d->ver));
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V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
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V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
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} else {
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V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
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V3D_PCTR_CYCLE_COUNT(v3d->ver));
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V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
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V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
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V3D_V3_PCTR_0_EN_ENABLE |
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1);
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}
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msleep(measure_ms);
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cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
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seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
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cycles,
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cycles / (measure_ms * 1000),
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(cycles / (measure_ms * 100)) % 10);
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return 0;
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}
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static int v3d_debugfs_mm(struct seq_file *m, void *unused)
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{
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struct drm_printer p = drm_seq_file_printer(m);
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struct drm_debugfs_entry *entry = m->private;
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struct drm_device *dev = entry->dev;
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struct v3d_dev *v3d = to_v3d_dev(dev);
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spin_lock(&v3d->mm_lock);
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drm_mm_print(&v3d->mm, &p);
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spin_unlock(&v3d->mm_lock);
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return 0;
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}
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static const struct drm_debugfs_info v3d_debugfs_list[] = {
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{"v3d_ident", v3d_v3d_debugfs_ident, 0},
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{"v3d_regs", v3d_v3d_debugfs_regs, 0},
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{"measure_clock", v3d_measure_clock, 0},
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{"bo_stats", v3d_debugfs_bo_stats, 0},
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{"v3d_mm", v3d_debugfs_mm, 0},
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};
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void
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v3d_debugfs_init(struct drm_minor *minor)
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{
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drm_debugfs_add_files(minor->dev, v3d_debugfs_list, ARRAY_SIZE(v3d_debugfs_list));
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}
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