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10d43ecbb0
The following functions have been in the mei code for
a long time but have never been used.
mei_txe_setup_satt2() was added in 2014 by
commit 32e2b59fca2c ("mei: txe: add hw-txe.c")
mei_me_cl_rm_by_uuid_id() was added in 2015 by
commit 79563db9ddd3 ("mei: add reference counting for me clients")
mei_cldev_uuid() was added in 2015 by
commit baeacd037697 ("mei: bus: export uuid and protocol version to mei_cl
bus drivers")
mei_cldev_recv_nonblock() was added in 2016 by
commit 076802d00615 ("mei: bus: enable non-blocking RX")
it is the only user of mei_cldev_recv_nonblock_vtag().
Remove them.
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Alexander Usyskin <alexander.usyskin@intel.com>
Link: https://lore.kernel.org/r/20250130012654.255119-1-linux@treblig.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2013-2016, Intel Corporation. All rights reserved.
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* Intel Management Engine Interface (Intel MEI) Linux driver
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*/
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#ifndef _MEI_HW_TXE_H_
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#define _MEI_HW_TXE_H_
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#include <linux/irqreturn.h>
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#include "hw.h"
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#include "hw-txe-regs.h"
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#define MEI_TXI_RPM_TIMEOUT 500 /* ms */
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/* Flatten Hierarchy interrupt cause */
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#define TXE_INTR_READINESS_BIT 0 /* HISR_INT_0_STS */
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#define TXE_INTR_READINESS HISR_INT_0_STS
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#define TXE_INTR_ALIVENESS_BIT 1 /* HISR_INT_1_STS */
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#define TXE_INTR_ALIVENESS HISR_INT_1_STS
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#define TXE_INTR_OUT_DB_BIT 2 /* HISR_INT_2_STS */
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#define TXE_INTR_OUT_DB HISR_INT_2_STS
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#define TXE_INTR_IN_READY_BIT 8 /* beyond HISR */
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#define TXE_INTR_IN_READY BIT(8)
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/**
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* struct mei_txe_hw - txe hardware specifics
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*
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* @mem_addr: SeC and BRIDGE bars
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* @aliveness: aliveness (power gating) state of the hardware
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* @readiness: readiness state of the hardware
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* @slots: number of empty slots
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* @wait_aliveness_resp: aliveness wait queue
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* @intr_cause: translated interrupt cause
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*/
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struct mei_txe_hw {
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void __iomem * const *mem_addr;
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u32 aliveness;
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u32 readiness;
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u32 slots;
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wait_queue_head_t wait_aliveness_resp;
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unsigned long intr_cause;
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};
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#define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw)
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static inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw)
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{
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return container_of((void *)hw, struct mei_device, hw);
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}
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struct mei_device *mei_txe_dev_init(struct pci_dev *pdev);
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irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id);
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irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id);
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int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req);
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#endif /* _MEI_HW_TXE_H_ */
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