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74934ddf12
This patch adds RDMA_TRANSPORT_RX and RDMA_TRANSPORT_TX as a new flow table type for matcher creation. Signed-off-by: Patrisious Haddad <phaddad@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Link: https://patch.msgid.link/2287d8c50483e880450c7e8e08d9de34cdec1b14.1741261611.git.leon@kernel.org Signed-off-by: Leon Romanovsky <leon@kernel.org>
121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
/*
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* Copyright (c) 2018, Mellanox Technologies inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_USER_IOCTL_VERBS_H
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#define MLX5_USER_IOCTL_VERBS_H
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#include <linux/types.h>
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enum mlx5_ib_uapi_flow_action_flags {
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MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA = 1 << 0,
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};
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enum mlx5_ib_uapi_flow_table_type {
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX = 0x0,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX = 0x1,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB = 0x2,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX = 0x3,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TX = 0x4,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TRANSPORT_RX = 0x5,
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MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TRANSPORT_TX = 0x6,
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};
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enum mlx5_ib_uapi_flow_action_packet_reformat_type {
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MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 = 0x0,
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MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x1,
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MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x2,
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MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x3,
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};
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enum mlx5_ib_uapi_reg_dmabuf_flags {
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MLX5_IB_UAPI_REG_DMABUF_ACCESS_DATA_DIRECT = 1 << 0,
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};
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struct mlx5_ib_uapi_devx_async_cmd_hdr {
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__aligned_u64 wr_id;
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__u8 out_data[];
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};
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enum mlx5_ib_uapi_dm_type {
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MLX5_IB_UAPI_DM_TYPE_MEMIC,
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MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM,
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MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM,
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MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM,
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MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM,
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};
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enum mlx5_ib_uapi_devx_create_event_channel_flags {
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MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0,
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};
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struct mlx5_ib_uapi_devx_async_event_hdr {
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__aligned_u64 cookie;
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__u8 out_data[];
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};
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enum mlx5_ib_uapi_pp_alloc_flags {
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MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX = 1 << 0,
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};
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enum mlx5_ib_uapi_uar_alloc_type {
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MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF = 0x0,
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MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC = 0x1,
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};
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enum mlx5_ib_uapi_query_port_flags {
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MLX5_IB_UAPI_QUERY_PORT_VPORT = 1 << 0,
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MLX5_IB_UAPI_QUERY_PORT_VPORT_VHCA_ID = 1 << 1,
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MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_RX = 1 << 2,
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MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_TX = 1 << 3,
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MLX5_IB_UAPI_QUERY_PORT_VPORT_REG_C0 = 1 << 4,
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MLX5_IB_UAPI_QUERY_PORT_ESW_OWNER_VHCA_ID = 1 << 5,
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};
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struct mlx5_ib_uapi_reg {
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__u32 value;
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__u32 mask;
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};
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struct mlx5_ib_uapi_query_port {
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__aligned_u64 flags;
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__u16 vport;
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__u16 vport_vhca_id;
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__u16 esw_owner_vhca_id;
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__u16 rsvd0;
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__aligned_u64 vport_steering_icm_rx;
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__aligned_u64 vport_steering_icm_tx;
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struct mlx5_ib_uapi_reg reg_c0;
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};
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#endif
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