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I/O memory is typically either mapped through direct calls to ioremap() or subsystem / bus specific ones such as pci_iomap(). Even though subsystem / bus specific functions to map I/O memory are based on ioremap() / iounmap() it is not desirable to re-implement them in Rust. Instead, implement a base type for I/O mapped memory, which generically provides the corresponding accessors, such as `Io::readb` or `Io:try_readb`. `Io` supports an optional const generic, such that a driver can indicate the minimal expected and required size of the mapping at compile time. Correspondingly, calls to the 'non-try' accessors, support compile time checks of the I/O memory offset to read / write, while the 'try' accessors, provide boundary checks on runtime. `IoRaw` is meant to be embedded into a structure (e.g. pci::Bar or io::IoMem) which creates the actual I/O memory mapping and initializes `IoRaw` accordingly. To ensure that I/O mapped memory can't out-live the device it may be bound to, subsystems must embed the corresponding I/O memory type (e.g. pci::Bar) into a `Devres` container, such that it gets revoked once the device is unbound. Reviewed-by: Alice Ryhl <aliceryhl@google.com> Tested-by: Daniel Almeida <daniel.almeida@collabora.com> Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com> Signed-off-by: Danilo Krummrich <dakr@kernel.org> Tested-by: Dirk Behme <dirk.behme@de.bosch.com> Link: https://lore.kernel.org/r/20241219170425.12036-8-dakr@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
102 lines
1.8 KiB
C
102 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/io.h>
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void __iomem *rust_helper_ioremap(phys_addr_t offset, size_t size)
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{
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return ioremap(offset, size);
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}
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void rust_helper_iounmap(volatile void __iomem *addr)
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{
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iounmap(addr);
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}
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u8 rust_helper_readb(const volatile void __iomem *addr)
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{
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return readb(addr);
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}
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u16 rust_helper_readw(const volatile void __iomem *addr)
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{
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return readw(addr);
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}
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u32 rust_helper_readl(const volatile void __iomem *addr)
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{
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return readl(addr);
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}
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#ifdef CONFIG_64BIT
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u64 rust_helper_readq(const volatile void __iomem *addr)
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{
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return readq(addr);
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}
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#endif
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void rust_helper_writeb(u8 value, volatile void __iomem *addr)
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{
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writeb(value, addr);
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}
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void rust_helper_writew(u16 value, volatile void __iomem *addr)
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{
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writew(value, addr);
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}
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void rust_helper_writel(u32 value, volatile void __iomem *addr)
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{
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writel(value, addr);
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}
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#ifdef CONFIG_64BIT
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void rust_helper_writeq(u64 value, volatile void __iomem *addr)
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{
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writeq(value, addr);
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}
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#endif
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u8 rust_helper_readb_relaxed(const volatile void __iomem *addr)
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{
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return readb_relaxed(addr);
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}
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u16 rust_helper_readw_relaxed(const volatile void __iomem *addr)
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{
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return readw_relaxed(addr);
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}
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u32 rust_helper_readl_relaxed(const volatile void __iomem *addr)
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{
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return readl_relaxed(addr);
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}
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#ifdef CONFIG_64BIT
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u64 rust_helper_readq_relaxed(const volatile void __iomem *addr)
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{
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return readq_relaxed(addr);
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}
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#endif
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void rust_helper_writeb_relaxed(u8 value, volatile void __iomem *addr)
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{
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writeb_relaxed(value, addr);
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}
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void rust_helper_writew_relaxed(u16 value, volatile void __iomem *addr)
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{
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writew_relaxed(value, addr);
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}
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void rust_helper_writel_relaxed(u32 value, volatile void __iomem *addr)
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{
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writel_relaxed(value, addr);
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}
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#ifdef CONFIG_64BIT
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void rust_helper_writeq_relaxed(u64 value, volatile void __iomem *addr)
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{
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writeq_relaxed(value, addr);
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}
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#endif
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