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377be47f90
If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-5-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
46 lines
1.2 KiB
Plaintext
46 lines
1.2 KiB
Plaintext
menu "Vendor extensions"
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config RISCV_ISA_VENDOR_EXT
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bool
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menu "Andes"
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config RISCV_ISA_VENDOR_EXT_ANDES
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bool "Andes vendor extension support"
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select RISCV_ISA_VENDOR_EXT
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default y
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help
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Say N here if you want to disable all Andes vendor extension
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support. This will cause any Andes vendor extensions that are
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requested by hardware probing to be ignored.
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If you don't know what to do here, say Y.
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endmenu
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menu "T-Head"
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config RISCV_ISA_VENDOR_EXT_THEAD
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bool "T-Head vendor extension support"
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select RISCV_ISA_VENDOR_EXT
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default y
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help
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Say N here to disable detection of and support for all T-Head vendor
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extensions. Without this option enabled, T-Head vendor extensions will
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not be detected at boot and their presence not reported to userspace.
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If you don't know what to do here, say Y.
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config RISCV_ISA_XTHEADVECTOR
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bool "xtheadvector extension support"
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depends on RISCV_ISA_VENDOR_EXT_THEAD
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depends on RISCV_ISA_V
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depends on FPU
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default y
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help
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Say N here if you want to disable all xtheadvector related procedures
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in the kernel. This will disable vector for any T-Head board that
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contains xtheadvector rather than the standard vector.
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If you don't know what to do here, say Y.
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endmenu
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endmenu
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