mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2025-04-09 14:45:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

coresight-tpdm: Add support to enable the lane for MCMB TPDM

Browse Source 
Add the sysfs file to set/get the enablement of the lane. For MCMB
configurations, the field "E_LN" in CMB_CR register is the
individual lane enables. MCMB lane N is enabled for trace
generation when M_CMB_CR.E=1 and M_CMB_CR.E_LN[N]=1. For lanes
that are not implemented on a given MCMB configuration, the
corresponding bits of this field read as 0 and ignore writes.

Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250226064008.2531037-4-quic_jinlmao@quicinc.com
This commit is contained in:
Tao Zhang 2025-02-25 22:40:08 -08:00 committed by Suzuki K Poulose
parent 07f7c21745
commit 0c0b6c05e2
3 changed files with 39 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
View File

@ -265,3 +265,10 @@ Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_t
Description:
(RW) Set/Get which lane participates in the output pattern
match cross trigger mechanism for the MCMB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select
Date: Feb 2025
KernelVersion 6.15
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Description:
(RW) Set/Get the enablement of the individual lane.

29
drivers/hwtracing/coresight/coresight-tpdm.c
View File

@ -1060,6 +1060,34 @@ static ssize_t mcmb_trig_lane_store(struct device *dev,
}
static DEVICE_ATTR_RW(mcmb_trig_lane);
static ssize_t mcmb_lanes_select_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
return sysfs_emit(buf, "%u\n",
(unsigned int)drvdata->cmb->mcmb.lane_select);
}
static ssize_t mcmb_lanes_select_store(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t size)
{
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
unsigned long val;
if (kstrtoul(buf, 0, &val) || (val & ~TPDM_MCMB_E_LN_MASK))
return -EINVAL;
guard(spinlock)(&drvdata->spinlock);
drvdata->cmb->mcmb.lane_select = val & TPDM_MCMB_E_LN_MASK;
return size;
}
static DEVICE_ATTR_RW(mcmb_lanes_select);
static struct attribute *tpdm_dsb_edge_attrs[] = {
&dev_attr_ctrl_idx.attr,
&dev_attr_ctrl_val.attr,
@ -1224,6 +1252,7 @@ static struct attribute *tpdm_cmb_msr_attrs[] = {
static struct attribute *tpdm_mcmb_attrs[] = {
&dev_attr_mcmb_trig_lane.attr,
&dev_attr_mcmb_lanes_select.attr,
NULL,
};

3
drivers/hwtracing/coresight/coresight-tpdm.h
View File

@ -48,6 +48,9 @@
/* MAX lanes in the output pattern for MCMB configurations*/
#define TPDM_MCMB_MAX_LANES 8
/* Filter bit 0~7 from the value for CR_E_LN */
#define TPDM_MCMB_E_LN_MASK GENMASK(7, 0)
/* DSB Subunit Registers */
#define TPDM_DSB_CR (0x780)
#define TPDM_DSB_TIER (0x784)