Tao Zhang 07f7c21745 coresight-tpdm: Add support to select lane ...

TPDM MCMB subunits supports up to 8 lanes CMB. For MCMB
configurations, the field "XTRIG_LNSEL" in CMB_CR register selects
which lane participates in the output pattern mach cross trigger
mechanism governed by the M_CMB_DXPR and M_CMB_XPMR regisers.

Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250226064008.2531037-3-quic_jinlmao@quicinc.com

2025-02-26 11:25:10 +00:00

..

coresight

coresight-tpdm: Add support to select lane

2025-02-26 11:25:10 +00:00

intel_th

intel_th: core: fix kernel-doc warnings

2025-01-13 06:18:47 +01:00

ptt

hwtracing: hisi_ptt: Assign parent for event_source device

2024-05-02 11:36:11 +01:00

stm

[tree-wide] finally take no_llseek out

2024-09-27 08:18:43 -07:00

Kconfig

hwtracing: hisi_ptt: Add trace function support for HiSilicon PCIe Tune and Trace device

2022-09-08 16:26:17 -06:00